The IBM Multi-input Flip Flop and my implementation - part 1

The basic flip flop in IBM's Solid Logic Technology has multiple modes in which it operates as well as characteristic behaviors that are relied upon heavily in the design of S/360 and 1130 computers. No modern logic gate provides these behaviors sufficient to put together a set of gates from an IBM ALD (automated logic diagram - the documentation of the circuitry of these computers.) I constructed several VHDL modules that I could instantiate and use as a direct substitute, thus producing the same results from a circuit I built with my modules and the circuits in the SLT generation equipment.

Most uses of the flip flop are purely asynchronous, with no clock applied that determines when the flip flop changes to its next state. This most common mode was level sensitive - what determined the output state of the flip flop was the static values of the inputs, much like a combinatorial gate such as an AND function is level sensitive and unclocked. Whenever the inputs A and B are both 1, the AND gate is at 1, this state occurs essentially immediately when the inputs become 1 and 1, and it persists outputing a steady 1 as long as the inputs remain at 1 and 1. For the IBM MI flip flop operated in this "DC" mode, if the set input is 1 then the flip flop virtually immediately flips on, its output now 1. If the reset input is 1, it will rapidly flip off, the output then being 0. The behavior is not well defined if both the set and reset are simultaneously 1. In a different mode ("AC"), the flip flip will toggle between on and off when the pair of input signals are both 1, but not so in the steady or DC mode that is used most widely.

This flip flop is used widely so that flip flops change state asynchronously whenever the input signals appear, in no particular relationship to the overall clock. Such flip flops might be turned on somewhere in the midst of a cycle, and might slop over before turning off well into a cycle after the one in which logical conditions dictate it should be reset.

To implement this DC mode (async, level sensitive) flip flop, very approximately like an SR latch in today's parlance, I had to build logic that would handle the bad situation (both set and reset simultaneously asserted).  This was essentially a pair of NOR gates, cross coupled so that the output of one gate was an input to the other. This provided both a normal and an inverted output (Q and Qnot).

If both inputs are asserted, the flip flop will act as if only the reset were asserted, as this was the safest condition for the flip flop to take if both S and R are 1.

The SLT system typically used inverted inputs for the flip flop, such that the flip flop is set if the set input is 0, while a 1 on the set input is ignored. Because the heart of SLT was diode logic coupled to an inverting transistor, all the gates had to be configurable to deal with both normal signal levels (1 is on) and inverted levels (0 is on). The outputs also had to be configured to be either inverted or normal type.

The 'flipflop' module offers generics that allow the inputs and independently the outputs to be inverted or normal, with the default condition inverted inputs and normal outputs if the generics were not overridden.

If a particular logic circuit in an ALD had some signals combined in an NAND gate to drive the set input of a flipflop and other signals combined, say, with a NOR gate to drive the reset, it would be represented in VHDL as:

  setsignal <= not (inputA and inputB and inputC);
  resetsignal <= not (inputD or inputE);
 setBBFF <= setsignal;
 resetBBFF <= resetsignal;

 . . . and later in the code I instantiated one of my flipflops to implement the DC mode behavior. It specifies inverted inputs, normal outputs, using signal SetBBFF as the 'set' input and ResetBBFF as the 'reset'. Its outputs are normal -  BB -- and inverted -- BBnot.

BBFF: FlipFlop
invinp => 1
J => SetBBFF,
K => ResetBBFF,
Q => BB,
Qnot => BBnot,
. . .
Working from ALDs, which named gates with two character codes such as AD, AE, AF, . . . I could directly code the combinatorial gates (A, OR, N, . . .)  and insert my flipflop modules in place of the flipflop types (FF). The reader could take the VHDL and match it very directly to the ALD logic, achieving one of the design principles which was to seek as exact a copy of the original 1130 logic as possible.

In this scheme, the normal combinatorial gates are directly implemented as modern logic functions ('and' and 'or'), since their behavior was consistent with SLT versions of those gates,  but the flip flop has to make use of my flipflop component.

My flipflop component behaved as the SLT FF did in DC mode, well enough that every function in the 1130 and peripherals I have implemented behaves just as intended, as described in the theory of operations manuals, and producing signal timings that match the documented 1130 results extremely well.

This was the simplest of the SLT gates to implement - next post will cover the "AC" mode flipflop, then pulse generators, delays and single shot triggers will be covered in later blog posts.

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