IBM Multi-Input Flip Flop and my implementation, part 2

The second major mode in which the SLT flip flop is used is what I will call edge-sensitive mode. In addition to the diodes that are tied together to form the "DC" logic gates - e.g. AND of three input signals - the flip flop has an input with a capacitor in series with a diode going into the same junction as the DC mode diodes. Further, it is set up so that the internal side of the capacitor is biased by another input line. This additional input line I call the 'gate' - while the input going through the capacitor I call the 'shift'.

Capacitors 'pass' current flow as the plates of the capacitor charge or discharge, based on changes in voltage across the device, but once the voltage stops changing, the current drops to zero. This makes a capacitor a differentiator, where the current passing through the device is the change in voltage rather than the absolute voltage level.

Because of the diodes in line with the capacitor and its placement relative to the gate electrode of the transistor inverter, it will change the state of the transistor for one specific direction of change - for convenience matching the widespread use in SLT circuits, we will talk about a flipflop whose 'set' input will only turn on if the voltage on the "AC mode" input shifts from 1 to 0. It becomes a falling edge detector, a current flowing to make a change in the flip flop only on the falling edge of that AC mode input. Further, if the bias on the internal side of the capacitor is set to a 0 level, then the falling edge won't generate the proper size and direction of current to trigger the flip flop, but if it was biased to 1, the shift down on the AC input to 0 produces the 'delta' or change current that activates the flip flop.

This is why I call the biasing input a 'gate' - if it is on, the flip flop AC input is going to activate whenever its signal falls from 1 to 0, right at the edge of the logic change. The AC input I call a 'shift' because it is the shift in the logic level from 1 to 0 that is detected. Together, we have a flip flop whose set and reset inputs could be configured with the AC mode inputs so that if some set of combinatorial conditions are true, the gate input is 1 and then it will activate at the precise timing defined by the logic change on the shift input.

In modern logic devices, one could imagine that if an input signal, not a clock, were to be hooked to the clock of a flipflop and if some other combinatorial logic (static level) signal were hooked to the input of the flip flop, then when the 'clock' edge was detected (the shift input) it would take on the state of the traditional input (our gate input) and produce an output that is true only when the gate is 1 and the shift provides the proper direction edge. This is not exactly the same, however, because in the IBM FF the set signal to the flip flop exists for only a short period of time then goes to zero, regardless of its prior state or to the state of the gate or other inputs.

Another way to imagine this part of the circuit is as an edge detector with an enable gate - if the gate input enables the detector, then when it detects an edge it emits a short duration pulse. With discrete circuits one could set up a time constant that produces the single shot positive going output pulse right at the time the edge is detected and only for a fixed time before it returns to zero where it will remain until some future edge, enabled by a suitable gate input, will trigger it again.

Producing signals of a fixed duration asynchronously with FPGAs is not reasonable. They are used to produce a fixed duration by counting cycles or stepping through state machines in a number of clock cycles with nice tidy synchronous designs.

My solution to this conundrum was to produce a hybrid - making use of clock synchronous logic to time out the output of the edge detector, but have the edge detected asynchronously. I had to mix async logic because the shift signal coming in might have its edge at any point, not just aligned with a clock tick of the FPGA. If the signal shift were happening very very close to the proper clock edge, we might violate setup or hold requirements of the hardware or be in an indeterminate state that causes glitchy behavior. Clock synchronous circuits need the non-clock signals to be stable surrounding the time of the clock edge, something that is part of the design thinking when creating such circuits. When you can't guarantee the alignment, you have to convert the inputs into a stable condition to make use of them.

My secret weapon is the huge advantage in speed I have with the FPGA compared to 1960s SLT technology. The cycle time of the FPGA board I am using for this project is 20 nanoseconds, while the T clock cycle time of the 1130 is 280 nanoseconds. This gives me the opportunity to use the hybrid logic in my edge-trigger flipflop to reliably detect the edge, ensure that the gate signal is stable at the time of the shift, then produce a one cycle output pulse as a sync operation. The delay at maximum is about 20 ns from when I complete deciding that we have the right conditions for the triggered condition, to align it with the next FPGA edge. Since the most basic of SLT gates has a delay time on the order of 30 nanoseconds, I ran a relatively small risk of delaying signals that go through edge triggers to make them too late for their next use. This risk is also made lower because the 1130 is not a clock sync design, so that if a signal triggers some state change 20 or 30 ns later than the 'clock' toggled, it still works since nothing is activated by a master clock tick.

Part of the design uses a flip flop with the shift signal used as the clock - this detects the edge, then sets a signal that or clock sync flip flop companion will use to step itself through the sync output generation. The gate signal might be changing right as the shift is detected or in the gap between when the async flipflop sees the edge and a bit later when the clock sync flipflop acts on it to produce a pulse. To protect against this, I route the gate signal through a chain of paired not gates (actually LUTs in the FPGA) and exclusive-or it with the live signal. This guarantees that it has not changed over the span of a handful of nanoseconds and is thus not an in-transition, changing gate that should not be acted upon.

There are a number of versions of this logic, as I have the need in some circuits to produce a pulse that is more than one cycle long to ensure I catch other signals safely in combinatorial logic further along in the 1130. In most cases, an AND or OR gate is edge-triggered, so that its combinatorial output is a pulse only active for the short duration after the shift input has its edge, rather than being a full flip flop. Thus, the edge triggered behavior was generalized and the output pulse of those is passed into the set or reset input of our other flipflip module to activate the change in flip flop state.

In IBM ALDs, the logic gates that are edge triggered are indicated only by a letter on one of the inputs - a P or an N - which declares that it is an AC mode, edge triggered input. In some circuit drawings, a capacitor symbol is placed on the line drawn for the input signal, but in other situations the only clue is the N or P on the logic gate box.

These edge triggers can have positive or inverted gate inputs (trigger only if the gate is 1 or if it is 0), they can detect the rising or falling edge (P or N trigger) of the shift, and they can emit a pulse that is positive going or one that is negative going. Thus, my modules that implement these gates are configurable with generic parameters to specify those variations, along with the duration of the pulse (in fpga cycles).

When writing VHDL to implement a page of the ALD that contains such edge triggered functions, I write the direct logic for normal combinatorial gates but instantiate my edge triggered module for each edge-triggered gate. It would look something like this in the code:

SFgate <= NotReadBit12;
SFshift <= NotCRReadRegLoadSP;

SG <= NotResetReadReg or NotDCReset or SB;

SetSKFF <= SF;
ResetSKFF <= SG;
            . . . . . . . .

  -- shift version of SH gate
SHG: EdgeTriggerGate
invgate => 1,
invshift => 1,
invout => 1
Gate => SHgate,
Shift => SHshift,
ClockMaster => ClockMaster,
Output => SH
-- SK flip flop
SKFF: FlipFlop
invinp => 1
J => SetSKFF,
K => ResetSKFF,
Q => SK,
Qnot => SKnot,
ClockMaster => ClockMaster

I set up the gate and shift inputs to SH, it is configured so that the gate and the shift are both inverted, as is the output pulse. That inverted output pulse of SH is what is used to set the flipflop SK, since its input signals are inverted too and a short term 0 inverted pulse from SH will turn on SK. The rest of SK flipflop is a static combinatorial signal that is written out and implemented by the FPGA in normal modern gates (or gates or their LUT equivalent). However, the edgetriggered gate and the flip flop will produce the SLT behavior by using my modules in the place of those gates from the ALD.

The IBM Flip Flop is even stranger than I am modeling, but fortunately those characteristics are not used in the 1130 design. The gate input to an edge sensitive gate will retain its asserted state for 90 ns after the input is removed, thus still allowing the gate to be triggered if the shift occurs during those 90 ns. That is three times the average combinatorial logic gate delay of SLT, long enough that a designer could make use of a signal that is no longer active, as long as it was asserted less than 90ns prior to the shift. Just to add to this, the gate must be held positive for a minimum of 170ns to guarantee that the shift is detected, which is almost half a T cycle long. In modern logic elements, if the delay of the gate is 1, the setup time is a small fraction of 1, not a multiple, and if a signal was deasserted its effect on the gate disappears in much less than 1 unit, compared to the delay time. 

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