SLT card recreation, IO Typewriter work and 1401 study, week ending May 31, 2014


Still working on the quality of the SPI link transfer between Arduino and fpga. More tweaks done but still it appears that the main problem is missed or doubled clock edges. This is partly a signal quality issue and partly an algorithm issue.


I received both boxes of miscellaneous Selectric parts purchased on ebay and these give me the missing springs and other items to continue reassembly and adjustment of the typewriter mechanism.So far I have replaced one of the missing springs and replaced a broken indicator that shows the column at which the carrier is sitting on the plastic scale on the front cover of the typewriter.

The rotate tape is now attached and the shift mechanism is partly reassembled. It required me to take apart some of the mechanism in the carrier, in order to get to the rotate drum directly. I have this reattached the mechanism and hooked up one end of the tilt tape, but have not yet hooked the tilt arm the carrier head.


I put together a power supply to give me the three voltages I need for SLT debugging - +6V, +3V and -3V - from the variable bench supply I owned which only offered two adjustable levels by itself. This card takes the 14V AC from the bench supply and produces the +6V. I then adjust the two sections of the bench supply to output +3 and -3 levels.

In addition to the test circuits, I needed a legitimate driving signal and a conforming SLT load for the outputs, to ensure that my circuit worked properly, obeyed the threshold voltages for switching and delivered adequate output levels under load. I took some example circuits for the driver and load from the documented test setup that IBM used to validate the operation of their logic circuits.

A full set of components are on order to build a complete prototype card - not on an SLT card but otherwise complete and ready for comparison to a live card. My simulation of the circuit we believe is on the card swings the output signal between +3 for logical one and -3V for logical zero. SLT logic uses ground for logical zero, not a negative value. However, this version of the card replaces other cards when the 1130 has a large memory configuration, requiring the memory to be moved to a different frame than its original placement. To span that longer distance the signals would run over coaxial cable.

I don't find any other place where IBM uses this pair of voltages and therefore have suspicions that something is wrong with the schematic. I will continue to stare at the pictures and try various alternatives until I get reasonable behavior. I also sent a detailed email to the museum with a standard SLT and-or-invert circuit they can use to test their cards and validate designs.


I began this week to set up some instructions and single cycle them through a 1401 system at CHM, allowing me to watch the operation and to reinforce my reading of the logic diagrams and training materials. A programmer would not need to know the level of detail I will need, because they don't need to understand how the various registers and circuitry changes in each cycle as long as the instruction does what it is defined to accomplish.

Just as an example, all numbers are stored in memory in BCD format and use the zone field of the low order digit to represent the arithmetic sign. However, the process of addition or subtraction involves converting the numbers from BCD (a decimal digit) to bi-quinary, and older mechanism simialr to an Abacus which represents digits as a units from five values (quinary) from 0 to 4 plus two values (binary) representing 0 or 1 fives. Thus, a seven is a 1(base2) and 2(base 5) while a 3 is 0(base 2) and 3(base 5).

The adder circuitry takes the two quinary values, producing a quinary result and possibly a carry. The carry is added along with the two binary values to form the new binary result, plus any carry is recorded as an overflow by the hardware. Being a bit more precise, the adder circuitry takes the two quinary values and the overflow from the addition of a prior digit, yielding a quinary result and the overflow to the binary section.

None of that is visible to the programmer nor does it show on the operator panel. All that is visible is the result of the addition translated back to BCD. An addition or subtraction operation proceeds in a non-obvious way. The low order digit is fetched from the A and B fields, taking a total of two execution cycles, for the sole purpose of examining the zone bits (B and A bits). If the two fields, A and B, are the same sign and we are adding, then the result will be the same sign as field B and addition will proceed in what IBM calls a 'true add'. However, if the two fields have different signs, we have to convert the B field to its tens-complement value before adding. Then, depending on which field is larger, retranslate the result back by another tens-complement.

Tens-complement takes each digit N and replaces it with 9-N, finally adding a 1 to the low order digit of the resulting field. The processor will walk backwards to lower addresses of the B field until it finds the word mark, converting each digit, then jump to the highest address (low order digit) of the field to resume doing the addition or subtraction.

Whether or not we took time to do the tens-complement of B, executing an addition proceeds by alternating fetchs of the A and B field values, bumping the addresses downwards (adjust by minus 1) and storing the result of the adder operation into B. These pairs continue until the word mark is reached on field B. If field A is shorter, once we hit its word mark the processor just plugs a zero in as the BCD value for the A field. Effectively, this extends the number with zeroes on the left to make it the same size as the B field.

At the end, if we did a complement add instead of a true add, the processor has to walk through the result to see if it has to be complemented again, then sets the zone value for the low order digit position of the B field. A particular position in the A and B fields might be fetched several times during a single addition. The zones may be compared to set the overall sign of the result, the fields may be examined to test a result for complementing, the field may be tens-complemented, or the fields may actually be added.

Doug Martin and I will spend some time on Monday cycling through instructions and confirming our understanding of the system. We are documenting this in order to build some training materials.

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