As part of my adapter for the IBM Electronic Typewriter Model 50 that I am connecting to the IBM 1130 replica, which maps the behavior and signals of the ET50 so that it appears to be an IO Selectric Keyboardless Printer, the device used as the IBM 1130's console printer. Since the ET50 does not have physical tab settings, instead having stored the tab as a flag in memory inside the typewriter control board, I have to mimic the tab function for full fidelity.
The 1130 console printer has a blue rectangular toggle switch which sets and clears the tab setting at the location where the typewriter carrier is sitting. It also has left and right margin settings that are physically implemented, but the ET50 did these purely in its 'software'. With no physical mechanism in place for either function, I am forced to build a logical tab array in my hardware adapter and keep track of the position of the left and right margins.
Setting and clearing tabs was straightforward, with a bit vector mapping the character positions across a line. If the bit is on, there is a tab set for that position on the line. Often a line will have multiple tabs set to allow the display of columnar data, issuing a tab command to skip the typewriter to the next tab position before typing the data for that column.
This involved some funny VHDL code - a process that continually produced a bit string by a shift right logical of a constant string consisting of a 1 followed by 132 '0' values. We shift right by the current carrier position amount, giving us a string with the 1 located at the current position and every other bit a zero. Simply OR that with the tab setting bit vector to add in a tab at this position. Invert this shifted string then AND it with the tab vector to clear the tab from this location.,
My carrier position is tracked by a light and phototransistor straddling a wheel with holes cut around the circle. As the carrier moves left or right, this wheel rotates and we count the number of pulses (holes) to know how far we have moved.
The machine resets at power up by slowly moving in reverse to the left side, continuing until there are no new pulses for 100ms. We move a tad to the right and establish this as position 0 of the line. Now, when we type a letter, we count pulses to space over to the next character position after the typeball strikes the ribbon. A tab operation is a continual movement to the right until we reach the position where a tab was set.
In software, it is easy to see how to implement this. Start at the position of the tab bit vector and count the zero entries until we reach the first '1' value. That tells us the number of positions to move to the right of our current (starting) place. Calculate the end position number for the tab, then move while counting pulses until we reach our target column. Because we start from our current carrier position, we always find the next non-zero value in the bit vector - the next tab position for the line - or discover there are no more tabs set.
In hardware, however, we don't have the cycles to iterate in a loop doing the counting - our algorithm is not parallel, it is sequential. Further, we would find the non-zero value and then do some arithmetic to compute the stop column for the tab - perhaps taking more cycles.
I had to design this so that it would produce the target column within one cycle, during the time we are executing the tab command and beginning carrier movement. I had to produce two bits of arcane logic to do this in parallel, actually doing it combinatorially not with clocked cycles.
The first logic had to resequence the bit vector so that our current position is at the beginning - we only care about how much further to move to our next tab, not about what was behind us. I used a function for this that takes a slice of the tab bit vector running from the current carrier position out to the end, then append extra '0' bits to ensure I have a full bit tab vector even when the carrier is near the right margin. That temporary result is returned from the function, which gives us the tab string as seen from the spot our carrier currently sits.
-- finds first 1 value in the first 128 bits and returns the position as integer
function NEXTTABS (input : std_logic_vector(0 to 130); here : integer) return std_logic_vector is
variable newvect : std_logic_vector(0 to 258);
constant zeroes : std_logic_vector(0 to 127) := (others => '0');
begin
newvect := input(here to 130) & zeroes;
return newvect(0 to 127);
end nexttabs;
An example of the smallest leaf logic for the leading zero detector circuit:
-- leading zero detector for a pair of bits of the input signal
entity LZD2 is
Port ( P0 : in STD_LOGIC;
P1 : in STD_LOGIC;
V : out STD_LOGIC;
P : out STD_LOGIC);
end LZD2;
architecture Behavioral of LZD2 is
begin
V <= P0 or P1;
P <= (not P0) and (P1);
end Behavioral;
This is cascaded together at the next level up in :
-- Leading zero detector module for four bits
entity LZD4 is
Port ( P0 : in STD_LOGIC;
P1 : in STD_LOGIC;
V0 : in STD_LOGIC;
V1 : in STD_LOGIC;
V : out STD_LOGIC;
P : out STD_LOGIC_VECTOR (0 to 1));
end LZD4;
architecture Behavioral of LZD4 is
signal selector : std_logic;
begin
V <= V0 or V1;
selector <= not V0;
P <=
selector & P0 when selector = '0' else
selector & P1;
end Behavioral;
this continues on up to the top of the cascade tree as:
-- Leading zero detector module for 128 bits
entity LZD128 is
Port ( P0 : in STD_LOGIC_VECTOR (0 to 5);
P1 : in STD_LOGIC_VECTOR (0 to 5);
V0 : in STD_LOGIC;
V1 : in STD_LOGIC;
V : out STD_LOGIC;
P : out STD_LOGIC_VECTOR (0 to 6));
end LZD128;
architecture Behavioral of LZD128 is
signal selector : std_logic;
begin
V <= V0 or V1;
selector <= not V0;
P <=
selector & P0 when selector = '0' else
selector & P1;
end Behavioral;
As soon as the carrier has stopped from its last movement, the sliced and rearranged bit vector goes through this cascade of gates and develops a valid binary pointer. This is added to the current carrier position value, that arithmetic occuring as soon as the point value stabilizes. The addition ripples through but is done long before a tab command is issued to the typewriter - thus we already have pre-computed the target location 'in case' we receive a tab command.
When the command is delivered from the 1130 console printer adapter to my logic, the execution is dead simple, setting this precomputed value as the target for a move. We fire a blank print cycle to start movement to the right, watching our carrier position until it reaches the target value, then we stop.
When you see the difference between the software (sequential) approach to this problem and the hardware (parallel) approach, you are beginning to think properly for good fpga design. It took me a while to break the software mindset and habits, so tempting to fall back on when the VHDL language allows procedural descriptions.
Below is the top level module for the leading zero detector circuitry. You can see how the modules are 'wired together' and produce a binary value that is the index of the first nonzero position.
-- implements the leading zero detector that will find and return the
-- position value of the first non-zero bit in a string of 128 bits
entity LZD is
Port ( Inbits : in STD_LOGIC_VECTOR (0 to 127);
Position : out STD_LOGIC_VECTOR (0 to 7));
end LZD;
architecture Behavioral of LZD is
signal pl2v0 : std_logic;
signal pl2v2 : std_logic;
signal pl2v4 : std_logic;
signal pl2v6 : std_logic;
signal pl2v8 : std_logic;
signal pl2v10 : std_logic;
signal pl2v12 : std_logic;
signal pl2v14 : std_logic;
signal pl2v16 : std_logic;
signal pl2v18 : std_logic;
signal pl2v20 : std_logic;
signal pl2v22 : std_logic;
signal pl2v24 : std_logic;
signal pl2v26 : std_logic;
signal pl2v28 : std_logic;
signal pl2v30 : std_logic;
signal pl2v32 : std_logic;
signal pl2v34 : std_logic;
signal pl2v36 : std_logic;
signal pl2v38 : std_logic;
signal pl2v40 : std_logic;
signal pl2v42 : std_logic;
signal pl2v44 : std_logic;
signal pl2v46 : std_logic;
signal pl2v48 : std_logic;
signal pl2v50 : std_logic;
signal pl2v52 : std_logic;
signal pl2v54 : std_logic;
signal pl2v56 : std_logic;
signal pl2v58 : std_logic;
signal pl2v60 : std_logic;
signal pl2v62 : std_logic;
signal pl2v64 : std_logic;
signal pl2v66 : std_logic;
signal pl2v68 : std_logic;
signal pl2v70 : std_logic;
signal pl2v72 : std_logic;
signal pl2v74 : std_logic;
signal pl2v76 : std_logic;
signal pl2v78 : std_logic;
signal pl2v80 : std_logic;
signal pl2v82 : std_logic;
signal pl2v84 : std_logic;
signal pl2v86 : std_logic;
signal pl2v88 : std_logic;
signal pl2v90 : std_logic;
signal pl2v92 : std_logic;
signal pl2v94 : std_logic;
signal pl2v96 : std_logic;
signal pl2v98 : std_logic;
signal pl2v100 : std_logic;
signal pl2v102 : std_logic;
signal pl2v104 : std_logic;
signal pl2v106 : std_logic;
signal pl2v108 : std_logic;
signal pl2v110 : std_logic;
signal pl2v112 : std_logic;
signal pl2v114 : std_logic;
signal pl2v116 : std_logic;
signal pl2v118 : std_logic;
signal pl2v120 : std_logic;
signal pl2v122 : std_logic;
signal pl2v124 : std_logic;
signal pl2v126 : std_logic;
signal vl2v0 : std_logic;
signal vl2v2 : std_logic;
signal vl2v4 : std_logic;
signal vl2v6 : std_logic;
signal vl2v8 : std_logic;
signal vl2v10 : std_logic;
signal vl2v12 : std_logic;
signal vl2v14 : std_logic;
signal vl2v16 : std_logic;
signal vl2v18 : std_logic;
signal vl2v20 : std_logic;
signal vl2v22 : std_logic;
signal vl2v24 : std_logic;
signal vl2v26 : std_logic;
signal vl2v28 : std_logic;
signal vl2v30 : std_logic;
signal vl2v32 : std_logic;
signal vl2v34 : std_logic;
signal vl2v36 : std_logic;
signal vl2v38 : std_logic;
signal vl2v40 : std_logic;
signal vl2v42 : std_logic;
signal vl2v44 : std_logic;
signal vl2v46 : std_logic;
signal vl2v48 : std_logic;
signal vl2v50 : std_logic;
signal vl2v52 : std_logic;
signal vl2v54 : std_logic;
signal vl2v56 : std_logic;
signal vl2v58 : std_logic;
signal vl2v60 : std_logic;
signal vl2v62 : std_logic;
signal vl2v64 : std_logic;
signal vl2v66 : std_logic;
signal vl2v68 : std_logic;
signal vl2v70 : std_logic;
signal vl2v72 : std_logic;
signal vl2v74 : std_logic;
signal vl2v76 : std_logic;
signal vl2v78 : std_logic;
signal vl2v80 : std_logic;
signal vl2v82 : std_logic;
signal vl2v84 : std_logic;
signal vl2v86 : std_logic;
signal vl2v88 : std_logic;
signal vl2v90 : std_logic;
signal vl2v92 : std_logic;
signal vl2v94 : std_logic;
signal vl2v96 : std_logic;
signal vl2v98 : std_logic;
signal vl2v100 : std_logic;
signal vl2v102 : std_logic;
signal vl2v104 : std_logic;
signal vl2v106 : std_logic;
signal vl2v108 : std_logic;
signal vl2v110 : std_logic;
signal vl2v112 : std_logic;
signal vl2v114 : std_logic;
signal vl2v116 : std_logic;
signal vl2v118 : std_logic;
signal vl2v120 : std_logic;
signal vl2v122 : std_logic;
signal vl2v124 : std_logic;
signal vl2v126 : std_logic;
signal pl4v0 : std_logic_vector(0 to 1);
signal pl4v4 : std_logic_vector(0 to 1);
signal pl4v8 : std_logic_vector(0 to 1);
signal pl4v12 : std_logic_vector(0 to 1);
signal pl4v16 : std_logic_vector(0 to 1);
signal pl4v20 : std_logic_vector(0 to 1);
signal pl4v24 : std_logic_vector(0 to 1);
signal pl4v28 : std_logic_vector(0 to 1);
signal pl4v32 : std_logic_vector(0 to 1);
signal pl4v36 : std_logic_vector(0 to 1);
signal pl4v40 : std_logic_vector(0 to 1);
signal pl4v44 : std_logic_vector(0 to 1);
signal pl4v48 : std_logic_vector(0 to 1);
signal pl4v52 : std_logic_vector(0 to 1);
signal pl4v56 : std_logic_vector(0 to 1);
signal pl4v60 : std_logic_vector(0 to 1);
signal pl4v64 : std_logic_vector(0 to 1);
signal pl4v68 : std_logic_vector(0 to 1);
signal pl4v72 : std_logic_vector(0 to 1);
signal pl4v76 : std_logic_vector(0 to 1);
signal pl4v80 : std_logic_vector(0 to 1);
signal pl4v84 : std_logic_vector(0 to 1);
signal pl4v88 : std_logic_vector(0 to 1);
signal pl4v92 : std_logic_vector(0 to 1);
signal pl4v96 : std_logic_vector(0 to 1);
signal pl4v100 : std_logic_vector(0 to 1);
signal pl4v104 : std_logic_vector(0 to 1);
signal pl4v108 : std_logic_vector(0 to 1);
signal pl4v112 : std_logic_vector(0 to 1);
signal pl4v116 : std_logic_vector(0 to 1);
signal pl4v120 : std_logic_vector(0 to 1);
signal pl4v124 : std_logic_vector(0 to 1);
signal vl4v0 : std_logic;
signal vl4v4 : std_logic;
signal vl4v8 : std_logic;
signal vl4v12 : std_logic;
signal vl4v16 : std_logic;
signal vl4v20 : std_logic;
signal vl4v24 : std_logic;
signal vl4v28 : std_logic;
signal vl4v32 : std_logic;
signal vl4v36 : std_logic;
signal vl4v40 : std_logic;
signal vl4v44 : std_logic;
signal vl4v48 : std_logic;
signal vl4v52 : std_logic;
signal vl4v56 : std_logic;
signal vl4v60 : std_logic;
signal vl4v64 : std_logic;
signal vl4v68 : std_logic;
signal vl4v72 : std_logic;
signal vl4v76 : std_logic;
signal vl4v80 : std_logic;
signal vl4v84 : std_logic;
signal vl4v88 : std_logic;
signal vl4v92 : std_logic;
signal vl4v96 : std_logic;
signal vl4v100 : std_logic;
signal vl4v104 : std_logic;
signal vl4v108 : std_logic;
signal vl4v112 : std_logic;
signal vl4v116 : std_logic;
signal vl4v120 : std_logic;
signal vl4v124 : std_logic;
signal pl8v0 : std_logic_vector(0 to 2);
signal pl8v8 : std_logic_vector(0 to 2);
signal pl8v16 : std_logic_vector(0 to 2);
signal pl8v24 : std_logic_vector(0 to 2);
signal pl8v32 : std_logic_vector(0 to 2);
signal pl8v40 : std_logic_vector(0 to 2);
signal pl8v48 : std_logic_vector(0 to 2);
signal pl8v56 : std_logic_vector(0 to 2);
signal pl8v64 : std_logic_vector(0 to 2);
signal pl8v72 : std_logic_vector(0 to 2);
signal pl8v80 : std_logic_vector(0 to 2);
signal pl8v88 : std_logic_vector(0 to 2);
signal pl8v96 : std_logic_vector(0 to 2);
signal pl8v104 : std_logic_vector(0 to 2);
signal pl8v112 : std_logic_vector(0 to 2);
signal pl8v120 : std_logic_vector(0 to 2);
signal vl8v0 : std_logic;
signal vl8v8 : std_logic;
signal vl8v16 : std_logic;
signal vl8v24 : std_logic;
signal vl8v32 : std_logic;
signal vl8v40 : std_logic;
signal vl8v48 : std_logic;
signal vl8v56 : std_logic;
signal vl8v64 : std_logic;
signal vl8v72 : std_logic;
signal vl8v80 : std_logic;
signal vl8v88 : std_logic;
signal vl8v96 : std_logic;
signal vl8v104 : std_logic;
signal vl8v112 : std_logic;
signal vl8v120 : std_logic;
signal pl16v0 : std_logic_vector(0 to 3);
signal pl16v16 : std_logic_vector(0 to 3);
signal pl16v32 : std_logic_vector(0 to 3);
signal pl16v48 : std_logic_vector(0 to 3);
signal pl16v64 : std_logic_vector(0 to 3);
signal pl16v80 : std_logic_vector(0 to 3);
signal pl16v96 : std_logic_vector(0 to 3);
signal pl16v112 : std_logic_vector(0 to 3);
signal vl16v0 : std_logic;
signal vl16v16 : std_logic;
signal vl16v32 : std_logic;
signal vl16v48 : std_logic;
signal vl16v64 : std_logic;
signal vl16v80 : std_logic;
signal vl16v96 : std_logic;
signal vl16v112 : std_logic;
signal pl32v0 : std_logic_vector(0 to 4);
signal pl32v32 : std_logic_vector(0 to 4);
signal pl32v64 : std_logic_vector(0 to 4);
signal pl32v96 : std_logic_vector(0 to 4);
signal vl32v0 : std_logic;
signal vl32v32 : std_logic;
signal vl32v64 : std_logic;
signal vl32v96 : std_logic;
signal pl64v0 : std_logic_vector(0 to 5);
signal pl64v64 : std_logic_vector(0 to 5);
signal vl64v0 : std_logic;
signal vl64v64 : std_logic;
signal pl128v0 : std_logic_vector(0 to 6);
signal vl128v0 : std_logic;
begin
lzd2g0 : lzd2
PORT MAP
( P0 => Inbits(0),
P1 => Inbits (1),
P => pl2v0,
V => vl2v0);
lzd2g2 : lzd2
PORT MAP
( P0 => Inbits(2),
P1 => Inbits (3),
P => pl2v2,
V => vl2v2);
lzd2g4 : lzd2
PORT MAP
( P0 => Inbits(4),
P1 => Inbits (5),
P => pl2v4,
V => vl2v4);
lzd2g6 : lzd2
PORT MAP
( P0 => Inbits(6),
P1 => Inbits (7),
P => pl2v6,
V => vl2v6);
lzd2g8 : lzd2
PORT MAP
( P0 => Inbits(8),
P1 => Inbits (9),
P => pl2v8,
V => vl2v8);
lzd2g10 : lzd2
PORT MAP
( P0 => Inbits(10),
P1 => Inbits (11),
P => pl2v10,
V => vl2v10);
lzd2g12 : lzd2
PORT MAP
( P0 => Inbits(12),
P1 => Inbits (13),
P => pl2v12,
V => vl2v12);
lzd2g14 : lzd2
PORT MAP
( P0 => Inbits(14),
P1 => Inbits (15),
P => pl2v14,
V => vl2v14);
lzd2g16 : lzd2
PORT MAP
( P0 => Inbits(16),
P1 => Inbits (17),
P => pl2v16,
V => vl2v16);
lzd2g18 : lzd2
PORT MAP
( P0 => Inbits(18),
P1 => Inbits (19),
P => pl2v18,
V => vl2v18);
lzd2g20 : lzd2
PORT MAP
( P0 => Inbits(20),
P1 => Inbits (21),
P => pl2v20,
V => vl2v20);
lzd2g22 : lzd2
PORT MAP
( P0 => Inbits(22),
P1 => Inbits (23),
P => pl2v22,
V => vl2v22);
lzd2g24 : lzd2
PORT MAP
( P0 => Inbits(24),
P1 => Inbits (25),
P => pl2v24,
V => vl2v24);
lzd2g26 : lzd2
PORT MAP
( P0 => Inbits(26),
P1 => Inbits (27),
P => pl2v26,
V => vl2v26);
lzd2g28: lzd2
PORT MAP
( P0 => Inbits(28),
P1 => Inbits (29),
P => pl2v28,
V => vl2v28);
lzd2g30 : lzd2
PORT MAP
( P0 => Inbits(30),
P1 => Inbits (31),
P => pl2v30,
V => vl2v30);
lzd2g32 : lzd2
PORT MAP
( P0 => Inbits(32),
P1 => Inbits (33),
P => pl2v32,
V => vl2v32);
lzd2g34 : lzd2
PORT MAP
( P0 => Inbits(34),
P1 => Inbits (35),
P => pl2v34,
V => vl2v34);
lzd2g36 : lzd2
PORT MAP
( P0 => Inbits(36),
P1 => Inbits (37),
P => pl2v36,
V => vl2v36);
lzd2g38 : lzd2
PORT MAP
( P0 => Inbits(38),
P1 => Inbits (39),
P => pl2v38,
V => vl2v38);
lzd2g40 : lzd2
PORT MAP
( P0 => Inbits(40),
P1 => Inbits (41),
P => pl2v40,
V => vl2v40);
lzd2g42 : lzd2
PORT MAP
( P0 => Inbits(42),
P1 => Inbits (43),
P => pl2v42,
V => vl2v42);
lzd2g44 : lzd2
PORT MAP
( P0 => Inbits(44),
P1 => Inbits (45),
P => pl2v44,
V => vl2v44);
lzd2g46 : lzd2
PORT MAP
( P0 => Inbits(46),
P1 => Inbits (47),
P => pl2v46,
V => vl2v46);
lzd2g48 : lzd2
PORT MAP
( P0 => Inbits(48),
P1 => Inbits (49),
P => pl2v48,
V => vl2v48);
lzd2g50 : lzd2
PORT MAP
( P0 => Inbits(50),
P1 => Inbits (51),
P => pl2v50,
V => vl2v50);
lzd2g52 : lzd2
PORT MAP
( P0 => Inbits(52),
P1 => Inbits (53),
P => pl2v52,
V => vl2v52);
lzd2g54 : lzd2
PORT MAP
( P0 => Inbits(54),
P1 => Inbits (55),
P => pl2v54,
V => vl2v54);
lzd2g56 : lzd2
PORT MAP
( P0 => Inbits(56),
P1 => Inbits (57),
P => pl2v56,
V => vl2v56);
lzd2g58 : lzd2
PORT MAP
( P0 => Inbits(58),
P1 => Inbits (59),
P => pl2v58,
V => vl2v58);
lzd2g60 : lzd2
PORT MAP
( P0 => Inbits(60),
P1 => Inbits (61),
P => pl2v60,
V => vl2v60);
lzd2g62 : lzd2
PORT MAP
( P0 => Inbits(62),
P1 => Inbits (63),
P => pl2v62,
V => vl2v62);
lzd2g64 : lzd2
PORT MAP
( P0 => Inbits(64),
P1 => Inbits (65),
P => pl2v64,
V => vl2v64);
lzd2g66 : lzd2
PORT MAP
( P0 => Inbits(66),
P1 => Inbits (67),
P => pl2v66,
V => vl2v66);
lzd2g68 : lzd2
PORT MAP
( P0 => Inbits(68),
P1 => Inbits (69),
P => pl2v68,
V => vl2v68);
lzd2g70 : lzd2
PORT MAP
( P0 => Inbits(70),
P1 => Inbits (71),
P => pl2v70,
V => vl2v70);
lzd2g72 : lzd2
PORT MAP
( P0 => Inbits(72),
P1 => Inbits (73),
P => pl2v72,
V => vl2v72);
lzd2g74 : lzd2
PORT MAP
( P0 => Inbits(74),
P1 => Inbits (75),
P => pl2v74,
V => vl2v74);
lzd2g76 : lzd2
PORT MAP
( P0 => Inbits(76),
P1 => Inbits (77),
P => pl2v76,
V => vl2v76);
lzd2g78 : lzd2
PORT MAP
( P0 => Inbits(78),
P1 => Inbits (79),
P => pl2v78,
V => vl2v78);
lzd2g80 : lzd2
PORT MAP
( P0 => Inbits(80),
P1 => Inbits (81),
P => pl2v80,
V => vl2v80);
lzd2g82 : lzd2
PORT MAP
( P0 => Inbits(82),
P1 => Inbits (83),
P => pl2v82,
V => vl2v82);
lzd2g84 : lzd2
PORT MAP
( P0 => Inbits(84),
P1 => Inbits (85),
P => pl2v84,
V => vl2v84);
lzd2g86 : lzd2
PORT MAP
( P0 => Inbits(86),
P1 => Inbits (87),
P => pl2v86,
V => vl2v86);
lzd2g88 : lzd2
PORT MAP
( P0 => Inbits(88),
P1 => Inbits (89),
P => pl2v88,
V => vl2v88);
lzd2g90 : lzd2
PORT MAP
( P0 => Inbits(90),
P1 => Inbits (91),
P => pl2v90,
V => vl2v90);
lzd2g92 : lzd2
PORT MAP
( P0 => Inbits(92),
P1 => Inbits (93),
P => pl2v92,
V => vl2v92);
lzd2g94 : lzd2
PORT MAP
( P0 => Inbits(94),
P1 => Inbits (95),
P => pl2v94,
V => vl2v94);
lzd2g96 : lzd2
PORT MAP
( P0 => Inbits(96),
P1 => Inbits (97),
P => pl2v96,
V => vl2v96);
lzd2g98 : lzd2
PORT MAP
( P0 => Inbits(98),
P1 => Inbits (99),
P => pl2v98,
V => vl2v98);
lzd2g100 : lzd2
PORT MAP
( P0 => Inbits(100),
P1 => Inbits (101),
P => pl2v100,
V => vl2v100);
lzd2g102 : lzd2
PORT MAP
( P0 => Inbits(102),
P1 => Inbits (103),
P => pl2v102,
V => vl2v102);
lzd2g104 : lzd2
PORT MAP
( P0 => Inbits(104),
P1 => Inbits (105),
P => pl2v104,
V => vl2v104);
lzd2g106 : lzd2
PORT MAP
( P0 => Inbits(106),
P1 => Inbits (107),
P => pl2v106,
V => vl2v106);
lzd2g108 : lzd2
PORT MAP
( P0 => Inbits(108),
P1 => Inbits (109),
P => pl2v108,
V => vl2v108);
lzd2g110 : lzd2
PORT MAP
( P0 => Inbits(110),
P1 => Inbits (111),
P => pl2v110,
V => vl2v110);
lzd2g112 : lzd2
PORT MAP
( P0 => Inbits(112),
P1 => Inbits (113),
P => pl2v112,
V => vl2v112);
lzd2g114 : lzd2
PORT MAP
( P0 => Inbits(114),
P1 => Inbits (115),
P => pl2v114,
V => vl2v114);
lzd2g116 : lzd2
PORT MAP
( P0 => Inbits(116),
P1 => Inbits (117),
P => pl2v116,
V => vl2v116);
lzd2g118 : lzd2
PORT MAP
( P0 => Inbits(118),
P1 => Inbits (119),
P => pl2v118,
V => vl2v118);
lzd2g120 : lzd2
PORT MAP
( P0 => Inbits(120),
P1 => Inbits (121),
P => pl2v120,
V => vl2v120);
lzd2g122 : lzd2
PORT MAP
( P0 => Inbits(122),
P1 => Inbits (123),
P => pl2v122,
V => vl2v122);
lzd2g124 : lzd2
PORT MAP
( P0 => Inbits(124),
P1 => Inbits (125),
P => pl2v124,
V => vl2v124);
lzd2g126 : lzd2
PORT MAP
( P0 => Inbits(126),
P1 => Inbits (127),
P => pl2v126,
V => vl2v126);
lzd4g0 : lzd4
PORT MAP
( P0 => pl2v0,
P1 => pl2v2,
V0 => vl2v0,
V1 => vl2v2,
P => pl4v0,
V => vl4v0);
lzd4g4 : lzd4
PORT MAP
( P0 => pl2v4,
P1 => pl2v6,
V0 => vl2v4,
V1 => vl2v6,
P => pl4v4,
V => vl4v4);
lzd4g8 : lzd4
PORT MAP
( P0 => pl2v8,
P1 => pl2v10,
V0 => vl2v8,
V1 => vl2v10,
P => pl4v8,
V => vl4v8);
lzd4g12 : lzd4
PORT MAP
( P0 => pl2v12,
P1 => pl2v14,
V0 => vl2v12,
V1 => vl2v14,
P => pl4v12,
V => vl4v12);
lzd4g16 : lzd4
PORT MAP
( P0 => pl2v16,
P1 => pl2v18,
V0 => vl2v16,
V1 => vl2v18,
P => pl4v16,
V => vl4v16);
lzd4g20 : lzd4
PORT MAP
( P0 => pl2v20,
P1 => pl2v22,
V0 => vl2v20,
V1 => vl2v22,
P => pl4v20,
V => vl4v20);
lzd4g24 : lzd4
PORT MAP
( P0 => pl2v24,
P1 => pl2v26,
V0 => vl2v24,
V1 => vl2v26,
P => pl4v24,
V => vl4v24);
lzd4g28 : lzd4
PORT MAP
( P0 => pl2v28,
P1 => pl2v30,
V0 => vl2v28,
V1 => vl2v30,
P => pl4v28,
V => vl4v28);
lzd4g32 : lzd4
PORT MAP
( P0 => pl2v32,
P1 => pl2v34,
V0 => vl2v32,
V1 => vl2v34,
P => pl4v32,
V => vl4v32);
lzd4g36 : lzd4
PORT MAP
( P0 => pl2v36,
P1 => pl2v38,
V0 => vl2v36,
V1 => vl2v38,
P => pl4v36,
V => vl4v36);
lzd4g40 : lzd4
PORT MAP
( P0 => pl2v40,
P1 => pl2v42,
V0 => vl2v40,
V1 => vl2v42,
P => pl4v40,
V => vl4v40);
lzd4g44 : lzd4
PORT MAP
( P0 => pl2v44,
P1 => pl2v46,
V0 => vl2v44,
V1 => vl2v46,
P => pl4v44,
V => vl4v44);
lzd4g48 : lzd4
PORT MAP
( P0 => pl2v48,
P1 => pl2v50,
V0 => vl2v48,
V1 => vl2v50,
P => pl4v48,
V => vl4v48);
lzd4g52 : lzd4
PORT MAP
( P0 => pl2v52,
P1 => pl2v54,
V0 => vl2v52,
V1 => vl2v54,
P => pl4v52,
V => vl4v52);
lzd4g56 : lzd4
PORT MAP
( P0 => pl2v56,
P1 => pl2v58,
V0 => vl2v56,
V1 => vl2v58,
P => pl4v56,
V => vl4v56);
lzd4g60 : lzd4
PORT MAP
( P0 => pl2v60,
P1 => pl2v62,
V0 => vl2v60,
V1 => vl2v62,
P => pl4v60,
V => vl4v60);
lzd4g64 : lzd4
PORT MAP
( P0 => pl2v64,
P1 => pl2v66,
V0 => vl2v64,
V1 => vl2v66,
P => pl4v64,
V => vl4v64);
lzd4g68 : lzd4
PORT MAP
( P0 => pl2v68,
P1 => pl2v70,
V0 => vl2v68,
V1 => vl2v70,
P => pl4v68,
V => vl4v68);
lzd4g72 : lzd4
PORT MAP
( P0 => pl2v72,
P1 => pl2v74,
V0 => vl2v72,
V1 => vl2v74,
P => pl4v72,
V => vl4v72);
lzd4g76 : lzd4
PORT MAP
( P0 => pl2v76,
P1 => pl2v78,
V0 => vl2v76,
V1 => vl2v78,
P => pl4v76,
V => vl4v76);
lzd4g80 : lzd4
PORT MAP
( P0 => pl2v80,
P1 => pl2v82,
V0 => vl2v80,
V1 => vl2v82,
P => pl4v80,
V => vl4v80);
lzd4g84 : lzd4
PORT MAP
( P0 => pl2v84,
P1 => pl2v86,
V0 => vl2v84,
V1 => vl2v86,
P => pl4v84,
V => vl4v84);
lzd4g88 : lzd4
PORT MAP
( P0 => pl2v88,
P1 => pl2v90,
V0 => vl2v88,
V1 => vl2v90,
P => pl4v88,
V => vl4v88);
lzd4g92 : lzd4
PORT MAP
( P0 => pl2v92,
P1 => pl2v94,
V0 => vl2v92,
V1 => vl2v94,
P => pl4v92,
V => vl4v92);
lzd4g96 : lzd4
PORT MAP
( P0 => pl2v96,
P1 => pl2v98,
V0 => vl2v96,
V1 => vl2v98,
P => pl4v96,
V => vl4v96);
lzd4g100 : lzd4
PORT MAP
( P0 => pl2v100,
P1 => pl2v102,
V0 => vl2v100,
V1 => vl2v102,
P => pl4v100,
V => vl4v100);
lzd4g104 : lzd4
PORT MAP
( P0 => pl2v104,
P1 => pl2v106,
V0 => vl2v104,
V1 => vl2v106,
P => pl4v104,
V => vl4v104);
lzd4g108 : lzd4
PORT MAP
( P0 => pl2v108,
P1 => pl2v110,
V0 => vl2v108,
V1 => vl2v110,
P => pl4v108,
V => vl4v108);
lzd4g112 : lzd4
PORT MAP
( P0 => pl2v112,
P1 => pl2v114,
V0 => vl2v112,
V1 => vl2v114,
P => pl4v112,
V => vl4v112);
lzd4g116 : lzd4
PORT MAP
( P0 => pl2v116,
P1 => pl2v118,
V0 => vl2v116,
V1 => vl2v118,
P => pl4v116,
V => vl4v116);
lzd4g120 : lzd4
PORT MAP
( P0 => pl2v120,
P1 => pl2v122,
V0 => vl2v120,
V1 => vl2v122,
P => pl4v120,
V => vl4v120);
lzd4g124 : lzd4
PORT MAP
( P0 => pl2v124,
P1 => pl2v126,
V0 => vl2v124,
V1 => vl2v126,
P => pl4v124,
V => vl4v124);
lzd8g0 : lzd8
PORT MAP
( P0 => pl4v0,
P1 => pl4v4,
V0 => vl4v0,
V1 => vl4v4,
P => pl8v0,
V => vl8v0);
lzd8g8 : lzd8
PORT MAP
( P0 => pl4v8,
P1 => pl4v12,
V0 => vl4v8,
V1 => vl4v12,
P => pl8v8,
V => vl8v8);
lzd8g16 : lzd8
PORT MAP
( P0 => pl4v16,
P1 => pl4v20,
V0 => vl4v16,
V1 => vl4v20,
P => pl8v16,
V => vl8v16);
lzd8g24 : lzd8
PORT MAP
( P0 => pl4v24,
P1 => pl4v28,
V0 => vl4v24,
V1 => vl4v28,
P => pl8v24,
V => vl8v24);
lzd8g32 : lzd8
PORT MAP
( P0 => pl4v32,
P1 => pl4v36,
V0 => vl4v32,
V1 => vl4v36,
P => pl8v32,
V => vl8v32);
lzd8g40 : lzd8
PORT MAP
( P0 => pl4v40,
P1 => pl4v44,
V0 => vl4v40,
V1 => vl4v44,
P => pl8v40,
V => vl8v40);
lzd8g48 : lzd8
PORT MAP
( P0 => pl4v48,
P1 => pl4v52,
V0 => vl4v48,
V1 => vl4v52,
P => pl8v48,
V => vl8v48);
lzd8g56 : lzd8
PORT MAP
( P0 => pl4v56,
P1 => pl4v60,
V0 => vl4v56,
V1 => vl4v60,
P => pl8v56,
V => vl8v56);
lzd8g64 : lzd8
PORT MAP
( P0 => pl4v64,
P1 => pl4v68,
V0 => vl4v64,
V1 => vl4v68,
P => pl8v64,
V => vl8v64);
lzd8g72 : lzd8
PORT MAP
( P0 => pl4v72,
P1 => pl4v76,
V0 => vl4v72,
V1 => vl4v76,
P => pl8v72,
V => vl8v72);
lzd8g80 : lzd8
PORT MAP
( P0 => pl4v80,
P1 => pl4v84,
V0 => vl4v80,
V1 => vl4v84,
P => pl8v80,
V => vl8v80);
lzd8g88 : lzd8
PORT MAP
( P0 => pl4v88,
P1 => pl4v92,
V0 => vl4v88,
V1 => vl4v92,
P => pl8v88,
V => vl8v88);
lzd8g96 : lzd8
PORT MAP
( P0 => pl4v96,
P1 => pl4v100,
V0 => vl4v96,
V1 => vl4v100,
P => pl8v96,
V => vl8v96);
lzd8g104 : lzd8
PORT MAP
( P0 => pl4v104,
P1 => pl4v108,
V0 => vl4v104,
V1 => vl4v108,
P => pl8v104,
V => vl8v104);
lzd8g112 : lzd8
PORT MAP
( P0 => pl4v112,
P1 => pl4v116,
V0 => vl4v112,
V1 => vl4v116,
P => pl8v112,
V => vl8v112);
lzd8g120 : lzd8
PORT MAP
( P0 => pl4v120,
P1 => pl4v124,
V0 => vl4v120,
V1 => vl4v124,
P => pl8v120,
V => vl8v120);
lzd16g0 : lzd16
PORT MAP
( P0 => pl8v0,
P1 => pl8v8,
V0 => vl8v0,
V1 => vl8v8,
P => pl16v0,
V => vl16v0);
lzd16g16 : lzd16
PORT MAP
( P0 => pl8v16,
P1 => pl8v24,
V0 => vl8v16,
V1 => vl8v24,
P => pl16v16,
V => vl16v16);
lzd16g32 : lzd16
PORT MAP
( P0 => pl8v32,
P1 => pl8v40,
V0 => vl8v32,
V1 => vl8v40,
P => pl16v32,
V => vl16v32);
lzd16g48 : lzd16
PORT MAP
( P0 => pl8v48,
P1 => pl8v56,
V0 => vl8v48,
V1 => vl8v56,
P => pl16v48,
V => vl16v48);
lzd16g64 : lzd16
PORT MAP
( P0 => pl8v64,
P1 => pl8v72,
V0 => vl8v64,
V1 => vl8v72,
P => pl16v64,
V => vl16v64);
lzd16g80 : lzd16
PORT MAP
( P0 => pl8v80,
P1 => pl8v88,
V0 => vl8v80,
V1 => vl8v88,
P => pl16v80,
V => vl16v80);
lzd16g96 : lzd16
PORT MAP
( P0 => pl8v96,
P1 => pl8v104,
V0 => vl8v96,
V1 => vl8v104,
P => pl16v96,
V => vl16v96);
lzd16g112 : lzd16
PORT MAP
( P0 => pl8v112,
P1 => pl8v120,
V0 => vl8v112,
V1 => vl8v120,
P => pl16v112,
V => vl16v112);
lzd32g0 : lzd32
PORT MAP
( P0 => pl16v0,
P1 => pl16v16,
V0 => vl16v0,
V1 => vl16v16,
P => pl32v0,
V => vl32v0);
lzd32g32 : lzd32
PORT MAP
( P0 => pl16v32,
P1 => pl16v48,
V0 => vl16v32,
V1 => vl16v48,
P => pl32v32,
V => vl32v32);
lzd32g64 : lzd32
PORT MAP
( P0 => pl16v64,
P1 => pl16v80,
V0 => vl16v64,
V1 => vl16v80,
P => pl32v64,
V => vl32v64);
lzd32g96 : lzd32
PORT MAP
( P0 => pl16v96,
P1 => pl16v112,
V0 => vl16v96,
V1 => vl16v112,
P => pl32v96,
V => vl32v96);
lzd64g0 : lzd64
PORT MAP
( P0 => pl32v0,
P1 => pl32v32,
V0 => vl32v0,
V1 => vl32v32,
P => pl64v0,
V => vl64v0);
lzd64g64 : lzd64
PORT MAP
( P0 => pl32v64,
P1 => pl32v96,
V0 => vl32v64,
V1 => vl32v96,
P => pl64v64,
V => vl64v64); lzd128g0 : lzd128
PORT MAP
( P0 => pl64v0,
P1 => pl64v64,
V0 => vl64v0,
V1 => vl64v64,
P => pl128v0,
V => vl128v0); position <=
"0" & pl128v0 when vl128v0 = '1' else
"10000000";
end Behavioral;
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