tag:blogger.com,1999:blog-79515737598489635172024-02-06T21:46:56.580-08:00IBM 1130 ProjectCarl Claunchhttp://www.blogger.com/profile/00359841432891565909noreply@blogger.comBlogger112125tag:blogger.com,1999:blog-7951573759848963517.post-86885543434576148672014-08-07T08:03:00.000-07:002014-10-26T09:00:03.848-07:00Slowdown on replica project until the real 1130 is restoredAfter discovering an 1130 system available for purchase in Kansas, I brought it back and am in the process of restoring it to operation. The retrieval and restoration effort is being documented in another blog - <a href="http://rescue1130.blogspot.com/">1130 rescue mission</a><br />
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UPDATE Oct 25: The 1131 is working, as is its keyboard and console printer (typewriter). The keypunch is working. The card reader and printer are partly restored, already partly operational.<br />
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When I restore each of the units, I can move it out to the large new shed outside that will be the permanent data center where the system will run. It will need to position the machines closer together than normally would be done, thus the doors and swing out gates of electronics can't be fully opened until I push boxes around on their rollers to get into whatever needs service. In normal operation, however, there will be enough room to move around and operate the system.<br />
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The 1130 system in the shed is compromised of:<br />
<ul>
<li>an expanded storage version of the main unit (1131) - 7' 6" wide by 2' 6" deep</li>
<li>a 1442 card reader/punch</li>
<li>an 1132 line printer</li>
<li>an additional disk drive (CHI 1105)</li>
<li>an 029 keypunch machine</li>
</ul>
Once the system itself is up and working, I hope to interface some of the peripherals that will also be used with the 1130 replica:<br />
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<ul>
<li>paper tape reader (appears to be IBM 1134)</li>
<li>paper tape punch (appears as an IBM 1055)</li>
<li>plotter (appears as an IBM 1627)</li>
<li>RK-05 drives as additional disk drives (appear to be 2310)</li>
<li>HP line printer (appears to be faster and less compute intensive 1403)</li>
<li>Documation card reader (appears to be less compute intensive 2501)</li>
<li>tape drive (will be custom device)</li>
</ul>
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I will document the inspection and restoration of the real 1130 on this blog, as well as resuming my replica activities after the system is out in its 'data center' shed. The replica will be more reliable, use far less power, and be more portable to bring to events such as the November 30 parties (11/30 in US formatted dates) that have been hosted by Brian Knittel and Norm Aleks in past years.Carl Claunchhttp://www.blogger.com/profile/00359841432891565909noreply@blogger.com0tag:blogger.com,1999:blog-7951573759848963517.post-50881310060803400282014-08-01T16:06:00.002-07:002014-08-01T16:06:35.493-07:00Surprise opportunity to pick up an IBM 1130 system - time for a road tripIn the middle of Kansas sits a room filled with twin 1130 systems, two 1132 printers, a 1442 reader/punch, plus keypunches, card sorters and other gear. On top of that, it comes with a ton of software on disk and punched card, what appears to be more than 200 boxes of unpunched card stock, paper, manuals and other goodies.<br />
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The owner used one of the systems to support his business, bought a second one when it was sold off by a local school to use as a backup, and kept them covered and protected from the day he switched them off until today. Due to a variety of circumstances, he needed to get these out of the storeroom before the end of this month. He contacted well known owners of a running 1130 system to see if they wanted to buy it; they in turn brought this to the attention of the 1130 enthusiasts on a google forum where I saw it.<br />
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I was able to react rapidly, collaborating with others on the list to allocate homes to the gear and, long story short, I will be in Kansas in less than a week, loading six tons of machinery, supplies and documentaiton onto a truck to drive back across the US to the west coast. Some of the equipment, like an 1132, sorter, collator and keypunch verifier, will go to a list member who lives near me, I will have an 1130 with 1442 and 1132, its HW documentation and plenty of supplies. Another set of 1130 collectors will have any manuals they don't currently own. The unpunched cards will mainly go to museums on the west coast as well a few esoteric machines. A van and trailer will depart Kansas in the opposite direction, bringing an 1131, Printronix printer and lots of computer room cabinetry to his collection on the east coast. With luck we can clean out the room in that one weekend, fitting it all on the 24' truck, the van and trailer. If not, we will have gotten close to all of it.<br />
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All the software that comes back will be uploaded to bitsavers and available for use on both physical and emulated 1130 systems everywhere. I hope to have the manuals which aren't currently shared online digitized and shared as well, although they are things I won't maintain control over after my return.<br />
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This will provide a very nice side by side testing capability for the fidelity of my 1130 replica - checking cycle by cycle as well as for identical timing and behavior. It may slow down my work on the faux peripherals - but some like the plotter can be interfaced to the real 1130 now as well as my replica. Same with the paper tape reader and punch units.<br />
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I get to spend part of the weekend assembling sheds to make room in my garage, with a larger shed coming in two weeks which will house my 1130 data center. Fortunately these sheds tuck away on the side of the house that is not visible to the street, neighbors and barely from inside the house.<br />
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I expect to document the operation from when I leave until the systems are in place and ready for restoration/bring upCarl Claunchhttp://www.blogger.com/profile/00359841432891565909noreply@blogger.com0tag:blogger.com,1999:blog-7951573759848963517.post-26642169209181643482013-12-31T11:12:00.000-08:002014-06-15T09:48:38.031-07:00Documenting the recreation of an IBM 1130 computer<div class="separator" style="clear: both; text-align: left;">
NEWEST POSTS AT END - this blog is sequenced with first post at top. To achieve this, I had to date the posts with false dates, this one at the end of 2013 and the ones below on earlier days. Thus the archive list on the bottom right of the blog will refer to Dec, Nov, Oct and Sep 2013 for the posts. To see more posts, go to bottom of page and click on "Older Posts" but for convenience, a list of the most recent are on the top right of this page. . </div>
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I have very fond memories of the IBM 1130 computer, as it was the first computer that I could spend hours on in the wee hours of the morning, after all the official work it had to process was completed. This helped me really grok the way it worked, stepping through programs and watching how it worked by way of the operator console, lights and switches primarily.<br />
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The system was produced in the same era as the IBM 360 series of mainframes, back in the 1960s, primarily using punched cards to submit programs and a high speed printer for the output of your work, but also providing a typewriter and keyboard that was used infrequently for certain programs or tasks.<br />
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It would be a blast to own one and toy with it for nostalgia, but impractical in several ways. Very few of these still exist, perhaps less than ten worldwide, and only two or three are even in operating condition. They are power hungry and space wasting - particularly when you add the card reader, keypunch to create the punched cards, line printer and other devices you need for a functional system. In some ways, the devices attached to the computer are as rare in their own light and challenging to acquire. My garage does not have room to host a working 1130 system, nor is it a high priority to spend the substantial amounts likely required to buy and restore the system.<br />
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Fortunately, modern technology has advanced incredibly far from the capabilities available decades ago. In a physical IBM 1130, the logic required hundreds of printed circuit boards each with dozens of components, while a single logic chip today can encompass all of the 1130 circuits and much more. Further, the speed of today's technology is so much faster that timing is not a challenge - no matter how complex a set of logical steps might be necessary to recreate the behavior of any circuit in the 1130, those steps can be stuck in the infinitessimal gaps between the glacially slow logic signals of the 1130, given the enormity of the speed advantage available today.<br />
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This blog will document my journey from desire to idea to recreated IBM 1130. It will not be a recreation in the sense that a museum would attempt, as that would seek to build a machine that looked almost identical to the real 1130 and used as close to identical parts and materials as is possible. Instead, my aim is to maximize the 1130 "experience", where I would be able to replicate the looks, sounds and behaviors from my youthful 1130 interactions, within some practical bounds.<br />
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The irony of that adjective - practical - will be apparent as you follow this journey to the recreation. As time went on, my threshold of practicality moved and moved again, involving more and more detailed recreations of the actual appearance and behavior. Not to spoil the reading of the blog too much, but at some point I decided I could recreate the console typewriter, the light panel, switches, buttons and keyboard. This involves modifying IBM Selectric typewriters, creating sheetmetal, formica enclosures, installing frosted lighted buttons and other details that drove up the project complexity and cost, but also increased the experiential fidelity and thus my ultimate satisfaction.<br />
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I had essentially zero hardware design experience or training at the outset of this project. I have poked and fooled with electrical and electronic items all my life, but with very limited understanding. I could look at simple circuits and understand them from a basic DC standpoint - trace the wiring and the switches. I had a rudimentary understanding of an RC constant but otherwise didn't grasp AC circuits at all. I understood basic logic gate types and ways to simplify or understand their connections, but that was nearly all I knew. Ohms law was the limit of my analytical toolkit for electronics. I could put kits together (thank you Heathkit and others) and could make crude modifications as long as I didn't need to calculate specific values or do too much engineering.<br />
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My entire working life I was exposed to hardware and would have loved to be capable of designing, modifying and deeply understanding it, but didn't have the skills. This project was a means of diving in and acquiring those skills, learning by doing, and having a driving goal that would keep me engaged until my understanding rose to levels where I could accomplish all the electronics tasks I had always wished I could accomplish.<br />
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The resulting designs and devices produced during this project are going to reflect this learning process. Some of the work will not be up to the standards of a working professional electronics engineer. As I built up skill in digital hardware design and VHDL coding, there were times when I used poor practices out of ignorance, or because I hadn't reached the skill level to properly see and implement the correct approach. I have tried to go back through the project periodically and improve sections more in line with current best practices.<br />
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This blog documents the 1130 effort, not the learning journey I undertook as a necessary part, but there will be places where I allude to my personal learning, perhaps covering some detail that is blindingly obvious to those readers who are experienced digital designers, but when it wasn't blindingly obvious to me as a tyro, I suspect it might not be obvious to the readers who are not engineering professionals.Carl Claunchhttp://www.blogger.com/profile/00359841432891565909noreply@blogger.com0tag:blogger.com,1999:blog-7951573759848963517.post-87076412067788625912013-12-29T12:29:00.000-08:002012-12-26T21:20:30.897-08:00From dream to idea and project - the triggerI am subscribed to the IBM1130 group on google groups and read with interest a post at the beginning of 2012 where a member mentioned a past hardware implementation of an 1130 using FPGA (field programmable logic array, a chip that can be structured to create almost any kind of hardware logic through programming).<br />
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Another member, Richard Stofer, replied that he was the creator and that his design was 'still available'. He had described it at an "IBM 1130 party" that was hosted once a year (on Nov 30th - 11/30) by the owners of one of the few remaining 1130s - Brian Knittel and Norm Aleks - http://ibm1130.org/. The annual parties no longer take place, sadly, but video clips of the last party in 2008 including a presentation by Richard Stofer about his project. In it, he described not only the design and the hardware he built, but the tools and products needed to do it.<br />
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Brian Knittel has built a software simulator of the 1130, available for download on their web site, that I was using to assuage my nostalgia. However, the simulator was not fully accurate, in that it didn't attempt to recreate the hardware console modes that I had used to single step my way through instructions to learn the 1130. <br />
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It was accurate from the view of software executing on the machine, whether it was user programs or the operating system - DMS2 - and other IBM provided software. It was not, however, accurate to a person who would have been working with the 1130, thus many buttons and switch settings did not work and some of the peripheral implementations were incomplete. For example, it is possible to use formats for punched cards that the 1130 simulator did not accomodate, since the software Brian wrote took input files that were either ascii 80 column images or 1130 binary format, but it was not dealing with the hollerith code (cards had punches in rows 12, 11, 0, 1, 2 . .. . 9 which in various patterns represented characters or data. The letter C was a punch in the 12 and 3 row of a column, for example. Thus, while a great pleasure to see the 'printed output' files created in ascii as I ran the 1130 and ran programs, it didn't satisfy the itch.<br />
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I contacted Richard who kindly agreed to share his designs and other information. I bought the hardware and acquired all the tools he described and created my own copy of his 1130 in fpga.<br />
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For those who care about the technical details, this paragraph will detail what was involved, otherwise skip to the following paragraph to continue. The design was implemented on a FPGA development board from Digilent (www.digilentinc.com), the Nexys2 with 1.2 million gate equivalents, written in VHDL which is one of the two main languages used to program hardware. Nexys2 is based on the Xilinx Spartan 3E FPGA and I had to install their ISE web edition development tools. In addition, I needed to program an MBED microcontroller to implement the emulation of the 1130's plotter (IBM 1627) which Richard accomplished by translating the plotter commands to the HPGL language from HP, used to drive their plotters (and the many HP normal page printers that support HPGL).<br />
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I built my version of Richard's fpga 1130 and learned a lot about logic design, VHDL and working with hardware. It was a bit more faithful to the 1130, but Richard did not have the same mania for an experiential recreation that drove my interests, he was focused on the fidelity to software, just as Brian was with his simulator, and did not implement the single cycle, single step and other modes I had hoped to recreate. His machine was an FPGA implementation of the Functional Characteristics, the manual that defined the way the machine would behave and is the main document that is used to provide the software level fidelity that was the aim of both Brian and Richard. In some ways, it was the simulator but built in hardware rather than software, although I want to be clear that this was an original effort by Richard that built the 1130 from the ground up from IBM documentation; it did not derive at all from Brian's simulator.<br />
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I worked with Richard on several improvements, both those I triggered and quite a few improvements that he created. We still swap ideas on ways that the fpga 1130 could be enhanced. The itch remained unsatisfied, however.<br />
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I discovered copies of some IBM manuals on a site called Bitsavers (www.bitsavers.org) that is preserving key historical documents and software from the earlier days of computing. Al Kossow drives that effort as well as serving as software curator at the Computer History Museum near me in Mountain View, CA. The FE Theory of Operation manual described enough about the way that the 1130 worked that I believed it might be possible to build a more faithful hardware version, one that would produce the same results on the console lights and support all the switch settings and buttons of the actual 1130. That trigger began my quest to build my hardware 1130.Carl Claunchhttp://www.blogger.com/profile/00359841432891565909noreply@blogger.com0tag:blogger.com,1999:blog-7951573759848963517.post-27706380115103464662013-12-28T17:05:00.000-08:002013-01-03T09:19:27.062-08:00Complications related to IBM technology used in 1130 - 1In order to recreate the 1130, I began researching the logic design and technology employed to build the 1130. This is the same technology IBM created to design and build their 360 series of mainframes - Solid Logic Technology (SLT). With enhancements as MST, it was used for their 370 generation as well.<br />
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A small bit of technology history is necessary to understand the reasons that IBM created SLT. These lead to the peculiarities that made my project more daunting than I had assumed when I began this quest a year ago. At the time that IBM was developing SLT for the upcoming "bet the company" S/360 launch, the industry was just transitioning from discrete transistors to integrated circuits in 1958, after the invention of the IC by Kilby at TI and by Noyce at Fairchild. For the first few years of the 1960s, ICs were very expensive and primarily used in aerospace and other defense areas where weight or other characteristics of the IC were all important. The industry was still debating the best way to build logic gates, with adherents promoting schemes such as DTL (diode oriented with transistors as active switches), TTL (transistor-transistor), and RTL (resistor-transistor). Traces of all these approaches are visible within SLT, which tends to the use of diodes and transistors in many of its building blocks. These were legitimate debates because the tradeoffs of speed, cost, size and power requirements were important choices when a large computer would fill a room just by itself. The eventual economics of ICs weren't obvious, as the industry was delivering small volumes at very high prices to demanding military specs that yielded many rejected chips during manufacture.<br />
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However, the cost advantages were obvious from reducing the number of discrete components on a board and the amount of wiring that had to occur between these parts. In addition, the circuits could operate faster because of shorter distances between the devices and other characteristics that reduced delays. IBM had to make some important choices then gamble on these by ramping up an entire supply chain from silicon to delivered computers that were based on the approach they would choose.<br />
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Had the choices been made just two or three years later, the core of SLT would undoubtedly have been different and based on integrated circuits. What IBM chose to base their entire next generation on was continued use of germanium transistors, diode oriented gates but to place the transistors and diodes on a ceramic substrate in little square modules.<br />
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<tr><td class="tr-caption" style="text-align: center;">SLT ceramic module built up with transistors, diodes and resistors</td></tr>
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A circuit board made with SLT consisted of a number of these ceramic squares, each containing some small number of transistor, resistor and diode devices wired together, and a fair amount of discrete traditional electronic components like resistors, crystals, transformers and capacitors to complete the desired function of the card.<br />
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<tr><td style="text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEh21bCzZLkdheUc0yOBBIgVvEUOOu3bymbHQwX4996CYFNCN_U5EQ81-kfwtxU0vSHkVmgQIaD1HC_HgjNZy_lhi26Q0qMaHZf3OnzO-ZxwtjpZNuynyHytOecZz9LbwrWWG4VCIGfRajY/s1600/680px-Slt1.jpg" imageanchor="1" style="margin-left: auto; margin-right: auto;"><img border="0" height="352" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEh21bCzZLkdheUc0yOBBIgVvEUOOu3bymbHQwX4996CYFNCN_U5EQ81-kfwtxU0vSHkVmgQIaD1HC_HgjNZy_lhi26Q0qMaHZf3OnzO-ZxwtjpZNuynyHytOecZz9LbwrWWG4VCIGfRajY/s400/680px-Slt1.jpg" width="400" /></a></td></tr>
<tr><td class="tr-caption" style="text-align: center;">Typical SLT card</td></tr>
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The SLT modules were portions of a logic gate or function, completed with external components or requiring more than one of the modules to comprise a single logic function such as a flip-flop. The basic module used most often in SLT has an AND gate, an OR gate and an inverter (NOT gate) inside in an arrangement they called AOI. Three diodes were wired together to form the AND function, that was joined to another diode that provide the OR function, and those four wired together diodes connect to a single transistor that is the inverter.<br />
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<tr><td class="tr-caption" style="text-align: center;">IBM's AOI module</td></tr>
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The flip flop used in many places in an 1130 or 360 computer required two AI (AND -Inverter) modules, a resistor pack (several resistors molded into one long component, and an RC pack (a mix of resistors and capacitors molded into one component).<br />
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Reading the IBM logic diagrams (called Automated Logic Diagrams or ALDs) requires you to understand how this technology works and how it is combined in modules on cards to make up logical functions that a modern digital designer would recognize.<br />
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This becomes much more difficult because IBM terminology at that time does not match the way that modern digital engineers refer to technology. IBM will refer to DC set or DC reset of a flip flop, or say that it is AC triggered (showing the connection on the ALD with a capacitor symbol just in front of the input), or refer to 'binary' triggering.<br />
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The IBM flip flop is not any of the well understood flip flop types a digital designer would recognize - not D, SR, or JK or other variants - and it has behaviors that are decidedly odd. If a flip flop is already in the 'on' state and a signal is applied to switch it on, the flip flop will produce a short pulse or signal from the opposite (off) output. This would wreak havoc with most designs if the engineer didn't expect it, as this would be a defect that would not be accepted from a modern logic component.<br />
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<tr><td class="tr-caption" style="text-align: center;">IBM Description of Flip Flop operation</td></tr>
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I had to do quite a bit of research and really understand what was going on, down inside the analog components in the SLT modules as well as in the digital designs shown in the SLTs. In order to do that, I would need to understand electronics and electrical engineering to a much deeper level than I had ever attained as a hobbyist/hacker/bludgeoner of electrical things. This leads to the next post - my pursuit of enough EE knowledge to move forward with the 1130 project.Carl Claunchhttp://www.blogger.com/profile/00359841432891565909noreply@blogger.com0tag:blogger.com,1999:blog-7951573759848963517.post-87295733750847156592013-12-26T19:26:00.000-08:002013-01-03T07:41:52.903-08:00Complications of the IBM technology in the 1130 - 2At just the right moment in time, when I realized that my skills in electrical circuits and electronics were woefully inadequate to the task ahead, Anant Agarwal at MIT was just launching his MITx educational initiative, beginning with a pilot course based upon the MIT 6002 course he teaches as the foundational EE course for MIT undergrads - Circuits and Electronics.<br />
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<a href="https://www.edx.org/courses/MITx/6.002x/2013_Spring/about">EdX 6002X course description</a><br />
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I joined that inaugural course of what has become EDx, expanding to a joint effort of MIT and Harvard under Dr. Agarwal's leadership. It was a great experience, often straining my very rusty math skills and forcing me learn new skills, for while I had done basic calculus years ago, I had to rapidly learn enough about matrix math, differential equation solving and other needed techniques to keep up with the class. </div>
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It was exactly what I needed, developing enough skill in both analog and digital circuit design that I was able to dive into this project and take on whatever need be done. I only wish I had learned this material when I was young - I would have had so much more success with all the projects and hobby activities I undertook over the years armed only with ohms law and some rudimentary awareness of electronics. </div>
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I was now able to understand what was occurring inside the SLT modules and in the 1130 machine. This wasn't the last hurdle, however, by a long shot. I will have to dive into a couple of technical subjects to properly communicate the basis of the new difficulties and complications. </div>
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Modern digital design strongly favors, almost insists upon designs that are clock synchronous - that a single master clock signal is used to control each change of state in the machine. Often, logical conditions (signals) must be used to determine whether a given state is turned on or what value should be output by a circuit. Synchronous designs need only ensure that the necessary signals have arrived sufficiently ahead of the 'tick' of the clock and will remain stable for a safety margin after that tick, then implement the state change or new data value exactly at the tick of the clock. </div>
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Alternative asynchronous design approaches, where the various signals are combined states change as soon as conditions align, can suffer from many problems. If one signal arrives early or late, the wrong value or new state might be implemented before all the intended conditions are in place. The output might waver between correct and incorrect values, short term signals might trigger changes that are undesired (glitches), and a successful async design needs careful attention to knowing and controlling the timing and duration of every involved signal. </div>
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The 1130 and 360 systems may have a system clock, but it is not used for synchronous logic. Rather, signals trigger a change of a flip flop as soon as they arrive. If conditions must be combined to determine what change to make, they must arrive at the proper time to avoid all the timing issues I discussed above. </div>
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At many places in the theory of operations manual, this is alluded to by comments such as "a slight overlap of I-cycle FFs may occur" or "the gates remain active, because of circuit delays, beyond the end of . . .". With clock synchronous designs, all the signals needed to determine the next cycle must be in place before the clock tick, but in the 360 era designs they can trigger the change whenever they arrive even partway into a cycle. </div>
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This would make it quite difficult to convert the design of the 1130 to a clock synchronous one, as some signals may not exist when they are needed. Possibly they could be created by a different set of logic so that they occur early enough to be used, but this is never universally true. </div>
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The next difficulty pertains to the choice of technology to build my 1130 - an FPGA. FPGAs are particularly unsuited to asynchronous designs and anyone designing logic for FPGAs learns that clock synchronous logic is almost essential for proper machine operation. The heart of an FPGA is the look up table, where all the input signals are used to address a set of values that become the output signals. The design does not use AND, OR and other gates, it instead codes the values for outputs that would be produced from some set of logic gates and uses the look up table to implement it. The design tools render a logic design into values to be loaded into the lookup tables (thus making it field programmable) and the implementation of given design may change each time the design is touched because the design tools makes different choices and assigns different locations for the lookup tables inside the FPGA chip. </div>
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What this means is that the timing delay for a signal is not well controllable by the designer. Further, techniques that are used to introduce delays using traditional gates are barely feasible with an FPGA.</div>
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If you wanted to build a 360 or 1130, the last technology you would consider would be an FPGA. </div>
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Between the strangely behaving logic technology, async design practices and unsuitability of FPGA for async and timing dependent purposes, this project was going to be much more work than it appeared when I began.</div>
Carl Claunchhttp://www.blogger.com/profile/00359841432891565909noreply@blogger.com0tag:blogger.com,1999:blog-7951573759848963517.post-59683702286683187032013-12-24T22:45:00.000-08:002013-01-03T09:09:57.946-08:00False starts and researchI began building the 1130 design several times over the past months, building up from the heart, the basic clocking, registers and arithmetic unit. Each time I reached a point where it became clear that the approach I was taking would not work, I tossed out all the code and hunted for a new idea that might work. I believe there were four fairly substantial starts that I discarded before I came on the idea for the current approach.<br />
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The four failed tries all attempted to create a clock synchronous design appropriate for FPGA instantiation, largely because I believed it was the only way the machine would work. I had copies of the IBM ALDs, the logic diagrams of the 1130, thanks to bitsavers.org, which up until then I was using as a reference source to understand what behavior I had to create, but not as a model for logic I would design. </div>
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<tr><td class="tr-caption" style="text-align: center;">Typical ALD page</td></tr>
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That meant quite a bit of research and analysis, digging through all the manuals and thinking about what was needed to make the machine function properly. What conditions would require data to move between a register pair, when to suppress normal activities, when to recognize error conditions . . . the deep detail that is needed to complete the design of a working computer. Once I had access to ALDs, I had another way to conduct research and was getting a fairly complete picture of the conditions, signals and what had to occur in which cycle for any instruction or condition. The list of what I didn't understand or what didn't yet make sense kept shrinking. For example, there is a ballet of tricks and special logic needed to create the Program Load behavior that the machine uses to bootstrap from a single boot card to end with the disk based monitor system running on the machine. How to force the store of each column from the card reader or paper tape reader, when the machine was not executing instructions? How to start the machine executing the first </div>
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instruction once the load of that first boot card was complete? You have to develop a very complete understanding of the interplay of signals and the normal operation of large parts of the machine before you can really understand what has to occur to do a Program Load. </div>
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This all changed a few months ago, triggered by a conversation I had with a collector who owns an 1130 and an 1800 - neither operational - and who is an engineer and creative hobbyist. I bought a paper tape reader on ebay and decided to pick it up locally because the seller was nearby. Bob Rosenbloom was that seller, and offered to show me his extensive computer and technology collection when I picked up the reader. Somewhere in the conversation, when he was showing me the start of his all-relay computer project and I was talking about the 1130 project, I mentioned the core challenge of building an async design in FPGA. Bob didn't this as an impossible thing at all and chatted about a similar issue he overcame several years back. </div>
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When I was back staring at the 1130 project notes, Bob's confidence that an async computer could be built successfully in an FPGA took hold. That was the first trigger. The second was my decision to implement the machine according to the original IBM design, attempting to build it as exactly to the ALD as possible. The third was the idea that I should build FPGA synchronous code to model any behaviors of the SLT logic that were not consistent with current logic, incompatible with FPGA or necessary. By encapsulating those behaviors in a virtual logic gate that I could combine with basic gates, I could build up logic that looked just like the ALDs and hopefully would behave the same way as well. </div>
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That method is working beautifully, now that I have all of the 1130 and most of its peripheral adapters implemented, have built emulators for most of the peripherals and am well along building up the other machinery to complete the working system. I have been debugging the machine steadily, making use of a logic analyzer as well as extensive use of the Xilinx logic simulator running on my laptop. It seems to be executing all instructions as well as IO interrupts perfectly, but I need to finish my peripheral emulation to get to where I can boot DMS and run card decks before I can finish debugging. There is a limit to how much I can hand assemble and load into the machine - I put in the core of the extended diagnostics, using the listings in the Maintenance Diagnostic Manuals (MDMs) that are also on Bitsavers. </div>
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I do need to relate a funny story about how well this is working and the dangers of using a single set of ALDs for a single 1130 machine.</div>
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The only complete set of ALDs on bitsavers is labeled 1130C. There is all but one volume of 1130B, but the missing volume is the crucial volume that contains most of the processor core. I was testing my machine, carefully implemented in my ALD-faithful approach, when I began chasing a defect. The 1130 steps through eight steps or cycles as part of one 'storage cycle' - the T clocks - stepping through T0 up to T7 in one storage cycle. The machine is designed to spend extra T7 cycles if doing variable length activities, such as addition or subtraction, which due to the 1130 approach will take more cycles for certain values of data than for others. My design was not moving directly from T7 of one cycle to T0 of the next, and I was struggling to figure out what I had done wrong to cause the behavior. Gradually it dawned on me that my machine was working exactly like the 1130C in real life would have operated, because that machine in real life was a special model, the slowed down model 4 that IBM sold as an entry price point. To justify the lower price point, the machine had some extra logic to spin its wheels a few cycles between T7 and the next T0, thus slowing down the performance. I had perfectly implemented that cycle wasting logic, because my ALD faithful, timing faithful machine was recreating an unusual slow model. Once I figured out what a normal machine would look like, such as the 1130B which was missing the pages that illustrated a full speed machine, I was able to get normal behavior for the machine I am recreating, a 2.2 microsecond storage cycle time 1130 with 32K of core.<br />
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The machine I have built is based on FPGA hardware, malleable hardware that is configured to produce a given hardware design with gates and wiring, the configuration stored on a read only memory that is loaded when power is applied. Make a change to the design, load a changed file to the read only memory, and the new hardware comes into being with a reset or power-on. The configuration is described in a language that circuit designers use to define and create products, with the two major choices being Verilog and VHDL. I chose VHDL and learned to build hardware using the language and the ISE tools from Xilinx <a href="http://www.xilinx.com/products/design-tools/ise-design-suite/ise-webpack.htm">ISE Webpack tools</a> that compile the VHDL, load it onto the board and provide simulation facilities to test out designs.<br />
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<tr><td style="text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjrXQ9H0y_dAu_JtwIbfRXrvTl4U3wd-xJ07sQD9vOk-mUgBn7gDiNgau9CcHr2U-r-gw3lUTkB_rZwlSDXlinpk1kKvLS1jIP7nCBKMpBO9LR2v5pxYtjiC3M9iY7CqHUZccjW5dZ0Xxw/s1600/images.jpg" imageanchor="1" style="margin-left: auto; margin-right: auto;"><img border="0" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjrXQ9H0y_dAu_JtwIbfRXrvTl4U3wd-xJ07sQD9vOk-mUgBn7gDiNgau9CcHr2U-r-gw3lUTkB_rZwlSDXlinpk1kKvLS1jIP7nCBKMpBO9LR2v5pxYtjiC3M9iY7CqHUZccjW5dZ0Xxw/s1600/images.jpg" /></a></td></tr>
<tr><td class="tr-caption" style="text-align: center;">FPGA chip - not the version used in my 1130</td></tr>
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The board on which the 1130 is implemented uses a Xilinx Spartan 3E FPGA (<a href="http://www.xilinx.com/support/documentation/data_sheets/ds312.pdf">datasheet</a>) that provides 1.2 million gate equivalents, far more than the total gates used in an 1130 and enough to support all the peripherals emulation and other additional logic I am adding to make the recreation a usable toy. </div>
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I will spend the next few posts talking about the unique behaviors and my little modules that stand in for logic gates in very place in the ALDs where the oddball behavior is needed. The only other changes I needed were to adjust a few spots where the machine is doing what IBM refers to as a "DC Reset" of a register. It is apparent that the response time of the SLT flip flop is s-l-o-w to such DC reset signals, thus the designers would be gating the movement of the current contents of a register to another spot while simultaneously doing a DC reset. Once I introduced a very minor delay (in terms of the FPGA clock which is 20ns compared to the IBM T cycles which are 280ns long), the current contents were copied successfully before the reset took effect. I expected many such timing issues that would need to be tracked down laboriously, but it was only a handful of adjustments that seemed necessary, everything else is operating very reliably.<br />
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It the spots where I introduced the delays, I see that IBM placed pairs of not gates, as they saw the need to introduce signal delays. Unfortunately, the FPGA design tools intelligently remove that, recognizing that in digital logic, two wrongs make a right - the final outcome is identical except for timing. Thus, the intended delay was removed. Even though the FPGA uses lookup tables instead of gates, if it did look up a NOT function twice it would have added some delay and might have done the trick, but my change does the delay explicitly in an encapsulated logic element I call a "delay".</div>
Carl Claunchhttp://www.blogger.com/profile/00359841432891565909noreply@blogger.com0tag:blogger.com,1999:blog-7951573759848963517.post-45444476922130345012013-12-21T20:59:00.000-08:002012-12-26T21:22:30.527-08:00The IBM Multi-input Flip Flop and my implementation - part 1The basic flip flop in IBM's Solid Logic Technology has multiple modes in which it operates as well as characteristic behaviors that are relied upon heavily in the design of S/360 and 1130 computers. No modern logic gate provides these behaviors sufficient to put together a set of gates from an IBM ALD (automated logic diagram - the documentation of the circuitry of these computers.) I constructed several VHDL modules that I could instantiate and use as a direct substitute, thus producing the same results from a circuit I built with my modules and the circuits in the SLT generation equipment.<br />
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Most uses of the flip flop are purely asynchronous, with no clock applied that determines when the flip flop changes to its next state. This most common mode was level sensitive - what determined the output state of the flip flop was the static values of the inputs, much like a combinatorial gate such as an AND function is level sensitive and unclocked. Whenever the inputs A and B are both 1, the AND gate is at 1, this state occurs essentially immediately when the inputs become 1 and 1, and it persists outputing a steady 1 as long as the inputs remain at 1 and 1. For the IBM MI flip flop operated in this "DC" mode, if the set input is 1 then the flip flop virtually immediately flips on, its output now 1. If the reset input is 1, it will rapidly flip off, the output then being 0. The behavior is not well defined if both the set and reset are simultaneously 1. In a different mode ("AC"), the flip flip will toggle between on and off when the pair of input signals are both 1, but not so in the steady or DC mode that is used most widely.<br />
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This flip flop is used widely so that flip flops change state asynchronously whenever the input signals appear, in no particular relationship to the overall clock. Such flip flops might be turned on somewhere in the midst of a cycle, and might slop over before turning off well into a cycle after the one in which logical conditions dictate it should be reset.<br />
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To implement this DC mode (async, level sensitive) flip flop, very approximately like an SR latch in today's parlance, I had to build logic that would handle the bad situation (both set and reset simultaneously asserted). This was essentially a pair of NOR gates, cross coupled so that the output of one gate was an input to the other. This provided both a normal and an inverted output (Q and Qnot).<br />
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If both inputs are asserted, the flip flop will act as if only the reset were asserted, as this was the safest condition for the flip flop to take if both S and R are 1.<br />
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The SLT system typically used inverted inputs for the flip flop, such that the flip flop is set if the set input is 0, while a 1 on the set input is ignored. Because the heart of SLT was diode logic coupled to an inverting transistor, all the gates had to be configurable to deal with both normal signal levels (1 is on) and inverted levels (0 is on). The outputs also had to be configured to be either inverted or normal type.<br />
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The 'flipflop' module offers generics that allow the inputs and independently the outputs to be inverted or normal, with the default condition inverted inputs and normal outputs if the generics were not overridden.<br />
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If a particular logic circuit in an ALD had some signals combined in an NAND gate to drive the set input of a flipflop and other signals combined, say, with a NOR gate to drive the reset, it would be represented in VHDL as:<br />
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setsignal <= not (inputA and inputB and inputC);<br />
resetsignal <= not (inputD or inputE);<br />
setBBFF <= setsignal;<br />
resetBBFF <= resetsignal;<br />
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. . . and later in the code I instantiated one of my flipflops to implement the DC mode behavior. It specifies inverted inputs, normal outputs, using signal SetBBFF as the 'set' input and ResetBBFF as the 'reset'. Its outputs are normal - BB -- and inverted -- BBnot.<br />
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<span class="Apple-tab-span" style="white-space: pre;"> </span>BBFF:<span class="Apple-tab-span" style="white-space: pre;"> </span>FlipFlop<br />
<span class="Apple-tab-span" style="white-space: pre;"> </span>GENERIC MAP (<br />
<span class="Apple-tab-span" style="white-space: pre;"> </span>invinp => 1<br />
<span class="Apple-tab-span" style="white-space: pre;"> </span>)<br />
<span class="Apple-tab-span" style="white-space: pre;"> </span>PORT MAP(<br />
<span class="Apple-tab-span" style="white-space: pre;"> </span>J => SetBBFF,<br />
<span class="Apple-tab-span" style="white-space: pre;"> </span>K => ResetBBFF,<br />
<span class="Apple-tab-span" style="white-space: pre;"> </span>Q => BB,<br />
<span class="Apple-tab-span" style="white-space: pre;"> </span>Qnot => BBnot,<br />
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Working from ALDs, which named gates with two character codes such as AD, AE, AF, . . . I could directly code the combinatorial gates (A, OR, N, . . .) and insert my flipflop modules in place of the flipflop types (FF). The reader could take the VHDL and match it very directly to the ALD logic, achieving one of the design principles which was to seek as exact a copy of the original 1130 logic as possible.<br />
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In this scheme, the normal combinatorial gates are directly implemented as modern logic functions ('and' and 'or'), since their behavior was consistent with SLT versions of those gates, but the flip flop has to make use of my flipflop component.<br />
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My flipflop component behaved as the SLT FF did in DC mode, well enough that every function in the 1130 and peripherals I have implemented behaves just as intended, as described in the theory of operations manuals, and producing signal timings that match the documented 1130 results extremely well.<br />
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This was the simplest of the SLT gates to implement - next post will cover the "AC" mode flipflop, then pulse generators, delays and single shot triggers will be covered in later blog posts.Carl Claunchhttp://www.blogger.com/profile/00359841432891565909noreply@blogger.com0tag:blogger.com,1999:blog-7951573759848963517.post-27020972120153259342013-12-18T19:44:00.000-08:002013-01-02T19:32:59.059-08:00IBM Multi-Input Flip Flop and my implementation, part 2The second major mode in which the SLT flip flop is used is what I will call edge-sensitive mode. In addition to the diodes that are tied together to form the "DC" logic gates - e.g. AND of three input signals - the flip flop has an input with a capacitor in series with a diode going into the same junction as the DC mode diodes. Further, it is set up so that the internal side of the capacitor is biased by another input line. This additional input line I call the 'gate' - while the input going through the capacitor I call the 'shift'.<br />
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Capacitors 'pass' current flow as the plates of the capacitor charge or discharge, based on changes in voltage across the device, but once the voltage stops changing, the current drops to zero. This makes a capacitor a differentiator, where the current passing through the device is the change in voltage rather than the absolute voltage level.<br />
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Because of the diodes in line with the capacitor and its placement relative to the gate electrode of the transistor inverter, it will change the state of the transistor for one specific direction of change - for convenience matching the widespread use in SLT circuits, we will talk about a flipflop whose 'set' input will only turn on if the voltage on the "AC mode" input shifts from 1 to 0. It becomes a falling edge detector, a current flowing to make a change in the flip flop only on the falling edge of that AC mode input. Further, if the bias on the internal side of the capacitor is set to a 0 level, then the falling edge won't generate the proper size and direction of current to trigger the flip flop, but if it was biased to 1, the shift down on the AC input to 0 produces the 'delta' or change current that activates the flip flop.<br />
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This is why I call the biasing input a 'gate' - if it is on, the flip flop AC input is going to activate whenever its signal falls from 1 to 0, right at the edge of the logic change. The AC input I call a 'shift' because it is the shift in the logic level from 1 to 0 that is detected. Together, we have a flip flop whose set and reset inputs could be configured with the AC mode inputs so that if some set of combinatorial conditions are true, the gate input is 1 and then it will activate at the precise timing defined by the logic change on the shift input.<br />
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In modern logic devices, one could imagine that if an input signal, not a clock, were to be hooked to the clock of a flipflop and if some other combinatorial logic (static level) signal were hooked to the input of the flip flop, then when the 'clock' edge was detected (the shift input) it would take on the state of the traditional input (our gate input) and produce an output that is true only when the gate is 1 and the shift provides the proper direction edge. This is not exactly the same, however, because in the IBM FF the set signal to the flip flop exists for only a short period of time then goes to zero, regardless of its prior state or to the state of the gate or other inputs.<br />
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Another way to imagine this part of the circuit is as an edge detector with an enable gate - if the gate input enables the detector, then when it detects an edge it emits a short duration pulse. With discrete circuits one could set up a time constant that produces the single shot positive going output pulse right at the time the edge is detected and only for a fixed time before it returns to zero where it will remain until some future edge, enabled by a suitable gate input, will trigger it again.<br />
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Producing signals of a fixed duration asynchronously with FPGAs is not
reasonable. They are used to produce a fixed duration by counting cycles or
stepping through state machines in a number of clock cycles with nice tidy
synchronous designs.<br />
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My solution to this conundrum was to produce a hybrid - making use of clock synchronous logic to time out the output of the edge detector, but have the edge detected asynchronously. I had to mix async logic because the shift signal coming in might have its edge at any point, not just aligned with a clock tick of the FPGA. If the signal shift were happening very very close to the proper clock edge, we might violate setup or hold requirements of the hardware or be in an indeterminate state that causes glitchy behavior. Clock synchronous circuits need the non-clock signals to be stable surrounding the time of the clock edge, something that is part of the design thinking when creating such circuits. When you can't guarantee the alignment, you have to convert the inputs into a stable condition to make use of them.<br />
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My secret weapon is the huge advantage in speed I have with the FPGA compared to 1960s SLT technology. The cycle time of the FPGA board I am using for this project is 20 nanoseconds, while the T clock cycle time of the 1130 is 280 nanoseconds. This gives me the opportunity to use the hybrid logic in my edge-trigger flipflop to reliably detect the edge, ensure that the gate signal is stable at the time of the shift, then produce a one cycle output pulse as a sync operation. The delay at maximum is about 20 ns from when I complete deciding that we have the right conditions for the triggered condition, to align it with the next FPGA edge. Since the most basic of SLT gates has a delay time on the order of 30 nanoseconds, I ran a relatively small risk of delaying signals that go through edge triggers to make them too late for their next use. This risk is also made lower because the 1130 is not a clock sync design, so that if a signal triggers some state change 20 or 30 ns later than the 'clock' toggled, it still works since nothing is activated by a master clock tick.<br />
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Part of the design uses a flip flop with the shift signal used as the clock - this detects the edge, then sets a signal that or clock sync flip flop companion will use to step itself through the sync output generation. The gate signal might be changing right as the shift is detected or in the gap between when the async flipflop sees the edge and a bit later when the clock sync flipflop acts on it to produce a pulse. To protect against this, I route the gate signal through a chain of paired not gates (actually LUTs in the FPGA) and exclusive-or it with the live signal. This guarantees that it has not changed over the span of a handful of nanoseconds and is thus not an in-transition, changing gate that should not be acted upon.<br />
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There are a number of versions of this logic, as I have the need in some circuits to produce a pulse that is more than one cycle long to ensure I catch other signals safely in combinatorial logic further along in the 1130. In most cases, an AND or OR gate is edge-triggered, so that its combinatorial output is a pulse only active for the short duration after the shift input has its edge, rather than being a full flip flop. Thus, the edge triggered behavior was generalized and the output pulse of those is passed into the set or reset input of our other flipflip module to activate the change in flip flop state.<br />
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In IBM ALDs, the logic gates that are edge triggered are indicated only by a letter on one of the inputs - a P or an N - which declares that it is an AC mode, edge triggered input. In some circuit drawings, a capacitor symbol is placed on the line drawn for the input signal, but in other situations the only clue is the N or P on the logic gate box.<br />
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These edge triggers can have positive or inverted gate inputs (trigger only if the gate is 1 or if it is 0), they can detect the rising or falling edge (P or N trigger) of the shift, and they can emit a pulse that is positive going or one that is negative going. Thus, my modules that implement these gates are configurable with generic parameters to specify those variations, along with the duration of the pulse (in fpga cycles).<br />
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When writing VHDL to implement a page of the ALD that contains such edge triggered functions, I write the direct logic for normal combinatorial gates but instantiate my edge triggered module for each edge-triggered gate. It would look something like this in the code:<br />
<br />
<br />
<br />
<span class="Apple-tab-span" style="white-space: pre;"> </span>SFgate <= NotReadBit12;<br />
<span class="Apple-tab-span" style="white-space: pre;"> </span>SFshift <= NotCRReadRegLoadSP;<br />
<span class="Apple-tab-span" style="white-space: pre;"> </span><br />
<span class="Apple-tab-span" style="white-space: pre;"> </span>SG <= NotResetReadReg or NotDCReset or SB;<br />
<span class="Apple-tab-span" style="white-space: pre;"> </span><span class="Apple-tab-span" style="white-space: pre;"> </span><br />
<span class="Apple-tab-span" style="white-space: pre;"> </span>SetSKFF <= SF;<br />
<span class="Apple-tab-span" style="white-space: pre;"> </span>ResetSKFF <= SG;<br />
. . . . . . . .<br />
<br />
<div class="MsoNormal">
<span lang="EN"> <span class="Apple-tab-span" style="white-space: pre;"> </span>-- shift version of SH gate<o:p></o:p></span></div>
<div class="MsoNormal">
<span class="Apple-tab-span" style="white-space: pre;"> </span>SHG: EdgeTriggerGate</div>
<div class="MsoNormal">
<span class="Apple-tab-span" style="white-space: pre;"> </span>GENERIC MAP (</div>
<div class="MsoNormal">
<span class="Apple-tab-span" style="white-space: pre;"> </span>invgate => 1,</div>
<div class="MsoNormal">
<span class="Apple-tab-span" style="white-space: pre;"> </span>invshift => 1,</div>
<div class="MsoNormal">
<span class="Apple-tab-span" style="white-space: pre;"> </span>invout => 1</div>
<div class="MsoNormal">
<span class="Apple-tab-span" style="white-space: pre;"> </span>)</div>
<div class="MsoNormal">
<span class="Apple-tab-span" style="white-space: pre;"> </span>PORT MAP(</div>
<div class="MsoNormal">
<span class="Apple-tab-span" style="white-space: pre;"> </span>Gate => SHgate,</div>
<div class="MsoNormal">
<span class="Apple-tab-span" style="white-space: pre;"> </span>Shift => SHshift,</div>
<div class="MsoNormal">
<span class="Apple-tab-span" style="white-space: pre;"> </span>ClockMaster => ClockMaster,</div>
<div class="MsoNormal">
<span class="Apple-tab-span" style="white-space: pre;"> </span>Output => SH</div>
<div class="MsoNormal">
<span class="Apple-tab-span" style="white-space: pre;"> </span>);</div>
<div class="MsoNormal">
<span class="Apple-tab-span" style="white-space: pre;"> </span></div>
<div>
<div>
<span class="Apple-tab-span" style="white-space: pre;"> </span>-- SK flip flop</div>
<div>
<span class="Apple-tab-span" style="white-space: pre;"> </span>SKFF:<span class="Apple-tab-span" style="white-space: pre;"> </span>FlipFlop</div>
<div>
<span class="Apple-tab-span" style="white-space: pre;"> </span>GENERIC MAP (</div>
<div>
<span class="Apple-tab-span" style="white-space: pre;"> </span>invinp => 1</div>
<div>
<span class="Apple-tab-span" style="white-space: pre;"> </span>)</div>
<div>
<span class="Apple-tab-span" style="white-space: pre;"> </span>PORT MAP(</div>
<div>
<span class="Apple-tab-span" style="white-space: pre;"> </span>J => SetSKFF,</div>
<div>
<span class="Apple-tab-span" style="white-space: pre;"> </span>K => ResetSKFF,</div>
<div>
<span class="Apple-tab-span" style="white-space: pre;"> </span>Q => SK,</div>
<div>
<span class="Apple-tab-span" style="white-space: pre;"> </span>Qnot => SKnot,</div>
<div>
<span class="Apple-tab-span" style="white-space: pre;"> </span>ClockMaster => ClockMaster</div>
<div>
<span class="Apple-tab-span" style="white-space: pre;"> </span>);</div>
</div>
<div>
<br /></div>
<div>
I set up the gate and shift inputs to SH, it is configured so that the gate and the shift are both inverted, as is the output pulse. That inverted output pulse of SH is what is used to set the flipflop SK, since its input signals are inverted too and a short term 0 inverted pulse from SH will turn on SK. The rest of SK flipflop is a static combinatorial signal that is written out and implemented by the FPGA in normal modern gates (or gates or their LUT equivalent). However, the edgetriggered gate and the flip flop will produce the SLT behavior by using my modules in the place of those gates from the ALD.<br />
<br />
The IBM Flip Flop is even stranger than I am modeling, but fortunately those characteristics are not used in the 1130 design. The gate input to an edge sensitive gate will retain its asserted state for 90 ns after the input is removed, thus still allowing the gate to be triggered if the shift occurs during those 90 ns. That is three times the average combinatorial logic gate delay of SLT, long enough that a designer could make use of a signal that is no longer active, as long as it was asserted less than 90ns prior to the shift. Just to add to this, the gate must be held positive for a minimum of 170ns to guarantee that the shift is detected, which is almost half a T cycle long. In modern logic elements, if the delay of the gate is 1, the setup time is a small fraction of 1, not a multiple, and if a signal was deasserted its effect on the gate disappears in much less than 1 unit, compared to the delay time. </div>
Carl Claunchhttp://www.blogger.com/profile/00359841432891565909noreply@blogger.com0tag:blogger.com,1999:blog-7951573759848963517.post-26365387237175187402013-12-15T19:02:00.000-08:002012-12-26T21:23:20.620-08:00Generalizing an edge sensitive async gateI generalized the "AC mode" described in the last post concerning the multi-input flip flop used in IBM SLT circuitry. This would be used anywhere that the designer wanted to fire off a control pulse that would activate some sequence of actions, with the timing for the emission of the pulse set by the 'shift' input to the gate and the enabling or disabling of the emission at that time controlled by the 'gate' input.<br />
<br />
This allowed the designer to make use of both long lasting signals reflecting logical conditions and of pulses to be driven at specific times. A signal such as "XIO instruction" might be on during most of the cycles when an XIO (execute input-output) instruction is active, and that could be one of the conditions that are combined to activate a specific circuit at some chosen time. If an XIO instruction of a certain type, such as a initiate read, is being executed, then we might want to cause the value read from memory to be set into a specific machine register. If that data is read during the E2 cycle while processing the instruction and the data is valid when the T3 cycle of E2 begins, we might have combinatorial logic mixing the 'XIO instruction' signal with signals for 'E2' and signals that identify this as an initiate-read type of XIO. Those relatively long lasting signals are used as the 'gate' input while the signal for being in a T3 cycle is used as the 'shift'. Our gate will fire a pulse if all of 'XIO instruction', 'E2' and "i nitiate read' are true, at the time that the T3 signal shifts from 0 to 1 (we begin the T3 cycle within the longer E2 cycle of the even longer single instruction XIO). This pulse from our gate might trigger the 'set' of a given register that will cause it to be loaded with the value just read from memory.<br />
<br />
This is how an async design can have vaguely clock-like cycles and cause some actions to happen at chosen times. Note that the pulse causing the loading of the register, in our example above, might occur at a time that has no specific relationship to other timings in the machine - it could be ahead or behind other pulses generated at the start of T3, as each portion of the machine operates solely based on pulses and signal levels it sees, unconstrained by any global synchronizing clock.<br />
<br />
I called this function EdgeGate and instantiate copies of this module for any gate in the 1130 design that is edge triggered. It receives a gate and a shift input, is secretly clocked by the FPGA master clock running at 50MHz, thus is able to produce a pulse of a chosen duration as its output. Fully configurable for the polarity of the inputs, the polarity of the output pulse and the duration in fpga cycles of the pulse itself.<br />
<br />
The entire VHDL of this function is posted for those readers who wish to see how it was implemented in more detail:<br />
<br />
<br />
library IEEE;<br />
use IEEE.STD_LOGIC_1164.ALL;<br />
entity EdgeTriggerGate is<br />
<span class="Apple-tab-span" style="white-space: pre;"> </span>Generic ( invgate : integer := 0;<br />
<span class="Apple-tab-span" style="white-space: pre;"> </span> invshift : integer := 0;<br />
<span class="Apple-tab-span" style="white-space: pre;"> </span>invout : integer := 0);<br />
Port ( Gate : in STD_LOGIC;<br />
Shift : in STD_LOGIC;<br />
ClockMaster : in STD_LOGIC;<br />
Output : out STD_LOGIC);end EdgeTriggerGate;<br />
<br />
architecture Behavioral of EdgeTriggerGate is<br />
<br />
<span class="Apple-tab-span" style="white-space: pre;"> </span>signal<span class="Apple-tab-span" style="white-space: pre;"> </span>Edge<span class="Apple-tab-span" style="white-space: pre;"> </span>:<span class="Apple-tab-span" style="white-space: pre;"> </span>std_logic<span class="Apple-tab-span" style="white-space: pre;"> </span>:= '0';<br />
<span class="Apple-tab-span" style="white-space: pre;"> </span>signal<span class="Apple-tab-span" style="white-space: pre;"> </span>Pulse :<span class="Apple-tab-span" style="white-space: pre;"> </span>std_logic<span class="Apple-tab-span" style="white-space: pre;"> </span>:= '0';<br />
<span class="Apple-tab-span" style="white-space: pre;"> </span>signal<span class="Apple-tab-span" style="white-space: pre;"> </span>Gated : std_logic := '0';<br />
<span class="Apple-tab-span" style="white-space: pre;"> </span>signal<span class="Apple-tab-span" style="white-space: pre;"> </span>Trigger : std_logic := '1';<br />
<span class="Apple-tab-span" style="white-space: pre;"> </span>signal<span class="Apple-tab-span" style="white-space: pre;"> </span>DelayedGate : std_logic := '1';<br />
<span class="Apple-tab-span" style="white-space: pre;"> </span>constant empty : integer := 0;<br />
<span class="Apple-tab-span" style="white-space: pre;"> </span><br />
begin<br />
<br />
<span class="Apple-tab-span" style="white-space: pre;"> </span>-- this just delays a copy of the gate signal, so that we can<br />
<span class="Apple-tab-span" style="white-space: pre;"> </span>-- verify that it is stable and not changing or glitching<br />
<span class="Apple-tab-span" style="white-space: pre;"> </span>DelayedGate <= not (not (not (not Gated))) after 2 ns;<br />
<span class="Apple-tab-span" style="white-space: pre;"> </span><br />
-- output is normal or inverse if wedged (invout /= 0)<br />
go1 : if invout = 0 generate<br />
<span class="Apple-tab-span" style="white-space: pre;"> </span>Output <= Pulse;<br />
<span class="Apple-tab-span" style="white-space: pre;"> </span>end generate;<br />
go2 : if invout /= 0 generate<br />
<span class="Apple-tab-span" style="white-space: pre;"> </span>Output <= not Pulse;<br />
<span class="Apple-tab-span" style="white-space: pre;"> </span>end generate;<br />
<br />
-- Level sensitive input is 0->1 edge (P) or inverse (N) if invshift /= 0<br />
gs1 : if invshift = 0 generate<br />
<span class="Apple-tab-span" style="white-space: pre;"> </span>Trigger <= Shift;<br />
<span class="Apple-tab-span" style="white-space: pre;"> </span>end generate;<br />
gs2 : if invshift /= 0 generate<br />
<span class="Apple-tab-span" style="white-space: pre;"> </span>Trigger <= not Shift;<br />
<span class="Apple-tab-span" style="white-space: pre;"> </span>end generate;<br />
<span class="Apple-tab-span" style="white-space: pre;"> </span><br />
-- Gating signals normal or inverse (wedged) if invgate /= 0<br />
gg1 : if invgate = 0 generate<br />
<span class="Apple-tab-span" style="white-space: pre;"> </span>Gated <= Gate;<br />
<span class="Apple-tab-span" style="white-space: pre;"> </span> end generate;<br />
gg2 : if invgate /= 0 generate<br />
<span class="Apple-tab-span" style="white-space: pre;"> </span>Gated <= not Gate;<br />
<span class="Apple-tab-span" style="white-space: pre;"> </span> end generate;<br />
<span class="Apple-tab-span" style="white-space: pre;"> </span><br />
<span class="Apple-tab-span" style="white-space: pre;"> </span>process (Trigger, Pulse, Gated, DelayedGate)<br />
<span class="Apple-tab-span" style="white-space: pre;"> </span>begin<br />
<span class="Apple-tab-span" style="white-space: pre;"> </span>if Pulse = '1' then<br />
<span class="Apple-tab-span" style="white-space: pre;"> </span>Edge <= '0';<br />
<span class="Apple-tab-span" style="white-space: pre;"> </span>elsif Trigger'event and Trigger = '1' and<br />
<span class="Apple-tab-span" style="white-space: pre;"> </span>(Gated and DelayedGate) = '1' then<br />
<span class="Apple-tab-span" style="white-space: pre;"> </span>Edge <= '1';<br />
<span class="Apple-tab-span" style="white-space: pre;"> </span>end if;<br />
<span class="Apple-tab-span" style="white-space: pre;"> </span>end process;<br />
<span class="Apple-tab-span" style="white-space: pre;"> </span><br />
<span class="Apple-tab-span" style="white-space: pre;"> </span>process (ClockMaster, Edge)<br />
<span class="Apple-tab-span" style="white-space: pre;"> </span>begin<br />
<span class="Apple-tab-span" style="white-space: pre;"> </span>if ClockMaster'event and ClockMaster = '1' then<br />
<span class="Apple-tab-span" style="white-space: pre;"> </span>Pulse <= Edge;<br />
<span class="Apple-tab-span" style="white-space: pre;"> </span>end if;<br />
<span class="Apple-tab-span" style="white-space: pre;"> </span>end process;<br />
<br />
end Behavioral;<br />
<div>
<br /></div>
Carl Claunchhttp://www.blogger.com/profile/00359841432891565909noreply@blogger.com0tag:blogger.com,1999:blog-7951573759848963517.post-5950683565652359422013-12-10T19:27:00.000-08:002012-12-26T21:23:46.500-08:00Other SLT gates I implemented that don't match standard fpga functionsSLT logic features some pulse producing circuit elements which are used in many places inside an 1130 or 360 computer. As these were built and controlled by selecting capacitors and RC networks on the SLT card, something not possible within an FPGA, they also needed to be modeled in a way that would produce the intended behavior. These modules I wrote to accomplish these functions are also instantiated in any code as a one to one substitute for the SLT elements in an ALD diagram. An ALD page could be represented by standard VHDL logic plus the substitute modules for FF, edge sensitive gates and these other element types, thus remaining very true to the circuit design.<br />
<br />
Single Shots (SS) are an SLT element that fires off a pulse of some duration chosen by the designer thru the specification of capacitor and resistor values to be connected to the element. For example, a given circuit might want a pulse of 250 microseconds duration to occur. The SS would fire a pulse whenever its input went on - it was edge sensitive. If the input remained on for a long time, it didn't matter, the pulse from the SS element would be 250 microseconds or whatever timing the designer chose. My module SingleShot is a variant written to provide a pure SS drop in substitute.<br />
<br />
Sample Pulse Driver (SPD) elements will take a logic signal and fire off a short pulse when the logic signal switches on. It is essentially an edge sensitive gate like my EdgeGate which has has a 'gate' input that is always true, thus it fires the pulse any and every time the 'shift' input produces the edge we are looking for.<br />
<br />
SS elements are behaviorally like SPD elements except the duration of the pulse is extended for some target interval in the SS, which could even be hundreds of milliseconds long; the SPD produces a short pulse about the speed of one gate delay in SLT terms.<br />
<br />
One final circuit need is for a delay, an element which will cause the signal to be delayed in time but otherwise follow the same pattern as the input signal. I wrote the Delay module as the means to cleanly insert a chosen delay into a circuit.<br />
<br />
The SingleShot and Delay modules are hybrids of async and clock sync techniques, much like the EdgeGate from which they are derived, since the triggers could arrive at any point unrelated to the master clock of the FPGA, even one as fast as the 20ns clock in our implementation board. The clock sync portion is used to produce given timings for pulse durations or delays of signals.<br />
<br />
Delay is used less than ten times in the entire 1130 implementation, since the 1130 designer implemented any desired delays by passing signals through several gates to introduce minor delays, not by placing a specific 'delay' type gate in the ALD. These were used only in the cases where signals had to be delayed for correct operation, something found to be very rare in the operation of the 1130 logic inside my recreation.<br />
<br />
Here is the SingleShot module for the reader interested in the details:<br />
<br />
<br />
library IEEE;<br />
use IEEE.STD_LOGIC_1164.ALL;<br />
use IEEE.NUMERIC_STD.ALL;<br />
<br />
--<span class="Apple-tab-span" style="white-space: pre;"> </span>This function will fire off a pulse of a preconfigured duration<br />
-- when the trigger edge arrives. It can be configured to trigger<br />
-- on the 0->1 or 1->0 edge, it can be configured to provide a positive<br />
-- or inverted pulse, and the duration is defined for the instance<br />
<br />
entity SingleShot is<br />
<span class="Apple-tab-span" style="white-space: pre;"> </span>Generic ( invtrigger : integer := 0;<br />
<span class="Apple-tab-span" style="white-space: pre;"> </span>invreset : integer := 0;<br />
<span class="Apple-tab-span" style="white-space: pre;"> </span>ctrload : integer := 1;<br />
<span class="Apple-tab-span" style="white-space: pre;"> </span>ctrsize : natural := 2;<br />
<span class="Apple-tab-span" style="white-space: pre;"> </span>invpulse : integer := 0);<br />
<span class="Apple-tab-span" style="white-space: pre;"> </span>Port ( Trigger : in STD_LOGIC;<br />
ClockMaster : in STD_LOGIC;<br />
<span class="Apple-tab-span" style="white-space: pre;"> </span> DCReset : in STD_LOGIC;<br />
Output : out STD_LOGIC);<br />
end SingleShot;<br />
<br />
architecture Behavioral of SingleShot is<br />
<br />
<span class="Apple-tab-span" style="white-space: pre;"> </span>signal<span class="Apple-tab-span" style="white-space: pre;"> </span>Pulse :<span class="Apple-tab-span" style="white-space: pre;"> </span>std_logic<span class="Apple-tab-span" style="white-space: pre;"> </span>:= '0';<br />
<span class="Apple-tab-span" style="white-space: pre;"> </span>signal<span class="Apple-tab-span" style="white-space: pre;"> </span>Shift :<span class="Apple-tab-span" style="white-space: pre;"> </span>std_logic;<br />
<span class="Apple-tab-span" style="white-space: pre;"> </span>signal<span class="Apple-tab-span" style="white-space: pre;"> </span>Edge :<span class="Apple-tab-span" style="white-space: pre;"> </span>std_logic;<br />
<span class="Apple-tab-span" style="white-space: pre;"> </span>signal<span class="Apple-tab-span" style="white-space: pre;"> </span>Reset :<span class="Apple-tab-span" style="white-space: pre;"> </span>std_logic;<br />
<span class="Apple-tab-span" style="white-space: pre;"> </span>signal<span class="Apple-tab-span" style="white-space: pre;"> </span>Ctr<span class="Apple-tab-span" style="white-space: pre;"> </span>: std_logic_vector(ctrsize-1 downto 0);<br />
<span class="Apple-tab-span" style="white-space: pre;"> </span>constant empty : integer := 0;<br />
begin<br />
-- output is positive going or inverse if wedged (invpulse /= 0)<br />
go1 : if invpulse = 0 generate<br />
<span class="Apple-tab-span" style="white-space: pre;"> </span>Output <= Pulse;<br />
<span class="Apple-tab-span" style="white-space: pre;"> </span>end generate;<br />
go2 : if invpulse /= 0 generate<br />
<span class="Apple-tab-span" style="white-space: pre;"> </span>Output <= not Pulse;<br />
<span class="Apple-tab-span" style="white-space: pre;"> </span>end generate;<br />
<br />
-- trigger is 0->1 edge (P) or inverse (N) if invtrigger /= 0<br />
gs1 : if invtrigger = 0 generate<br />
<span class="Apple-tab-span" style="white-space: pre;"> </span>Shift <= Trigger;<br />
<span class="Apple-tab-span" style="white-space: pre;"> </span>end generate;<br />
gs2 : if invtrigger /= 0 generate<br />
<span class="Apple-tab-span" style="white-space: pre;"> </span>Shift <= not Trigger;<br />
<span class="Apple-tab-span" style="white-space: pre;"> </span>end generate;<br />
<br />
-- set up for either pos or inverted reset as requested by caller<br />
gr1 : if invreset = 0 generate<br />
<span class="Apple-tab-span" style="white-space: pre;"> </span>Reset <= DCReset;<br />
<span class="Apple-tab-span" style="white-space: pre;"> </span>end generate;<br />
gr2 : if invreset /= 0 generate<br />
<span class="Apple-tab-span" style="white-space: pre;"> </span>Reset <= not DCReset;<br />
end generate;<br />
<span class="Apple-tab-span" style="white-space: pre;"> </span><br />
<span class="Apple-tab-span" style="white-space: pre;"> </span>process (Shift, Pulse, Reset)<br />
<span class="Apple-tab-span" style="white-space: pre;"> </span>begin<br />
<span class="Apple-tab-span" style="white-space: pre;"> </span>-- make sure we don't do anything bad at startup like emit or trigger spuriously<br />
<span class="Apple-tab-span" style="white-space: pre;"> </span>if Reset = '1' then<br />
<span class="Apple-tab-span" style="white-space: pre;"> </span>Edge <= '0';<br />
<span class="Apple-tab-span" style="white-space: pre;"> </span>-- if we started emitting an output pulse, shut down detection signal<br />
<span class="Apple-tab-span" style="white-space: pre;"> </span>elsif Pulse = '1' then<br />
<span class="Apple-tab-span" style="white-space: pre;"> </span>Edge <= '0';<br />
<span class="Apple-tab-span" style="white-space: pre;"> </span>-- if our shift occured and we are not already emitting, signal we should start<br />
<span class="Apple-tab-span" style="white-space: pre;"> </span>elsif Shift'event and Shift = '1'<br />
<span class="Apple-tab-span" style="white-space: pre;"> </span>and Ctr = std_logic_vector(to_unsigned(empty,ctrsize)) then<br />
<span class="Apple-tab-span" style="white-space: pre;"> </span>Edge <= '1';<br />
<span class="Apple-tab-span" style="white-space: pre;"> </span>end if;<br />
<span class="Apple-tab-span" style="white-space: pre;"> </span>end process;<br />
<span class="Apple-tab-span" style="white-space: pre;"> </span><br />
<span class="Apple-tab-span" style="white-space: pre;"> </span>process (ClockMaster, Ctr, Edge, Reset)<br />
<span class="Apple-tab-span" style="white-space: pre;"> </span>begin<br />
<span class="Apple-tab-span" style="white-space: pre;"> </span>-- at startup, make sure we don't trigger or emit anything spurious<br />
<span class="Apple-tab-span" style="white-space: pre;"> </span>if Reset = '1' then<br />
<span class="Apple-tab-span" style="white-space: pre;"> </span>Ctr <= (others => '0');<br />
<span class="Apple-tab-span" style="white-space: pre;"> </span>Pulse <= '0';<br />
<span class="Apple-tab-span" style="white-space: pre;"> </span>-- we detected an edge, load our counter and indicate we are emitting<br />
<span class="Apple-tab-span" style="white-space: pre;"> </span>elsif Edge = '1' then<br />
<span class="Apple-tab-span" style="white-space: pre;"> </span>Ctr <= std_logic_vector(to_unsigned(ctrload,ctrsize));<br />
<span class="Apple-tab-span" style="white-space: pre;"> </span>Pulse <= '1';<br />
<span class="Apple-tab-span" style="white-space: pre;"> </span>-- do our clock synchronous thing with the counter<br />
<span class="Apple-tab-span" style="white-space: pre;"> </span>elsif ClockMaster'event and ClockMaster = '1' then<br />
<span class="Apple-tab-span" style="white-space: pre;"> </span>-- if we have a positive count, decrement it and keep emitting<br />
<span class="Apple-tab-span" style="white-space: pre;"> </span>If to_integer( unsigned(ctr)) /= 0 then<br />
<span class="Apple-tab-span" style="white-space: pre;"> </span>Pulse <= '1';<br />
<span class="Apple-tab-span" style="white-space: pre;"> </span>Ctr <= std_logic_vector(<br />
<span class="Apple-tab-span" style="white-space: pre;"> </span>to_unsigned((to_integer( unsigned(ctr) ) - 1 ),ctrsize));<br />
<span class="Apple-tab-span" style="white-space: pre;"> </span>-- otherwise we are done, shut off pulse<br />
<span class="Apple-tab-span" style="white-space: pre;"> </span>else<br />
<span class="Apple-tab-span" style="white-space: pre;"> </span>Pulse <= '0';<br />
<span class="Apple-tab-span" style="white-space: pre;"> </span>end if;<br />
<span class="Apple-tab-span" style="white-space: pre;"> </span>end if;<br />
<span class="Apple-tab-span" style="white-space: pre;"> </span>end process;<br />
<br />
end Behavioral;Carl Claunchhttp://www.blogger.com/profile/00359841432891565909noreply@blogger.com0tag:blogger.com,1999:blog-7951573759848963517.post-21858839107537648082013-12-08T20:40:00.000-08:002013-01-19T08:11:54.874-08:00Hardware involved in the project as of Dec 2012The 1130 recreation is centered on a Digilent Nexys2 development board which contains a 1.2M gate equivalent FPGA - Xilinx Spartan 3E - plus support circuits and components, many of which I am leveraging.<br />
<br />
<table align="center" cellpadding="0" cellspacing="0" class="tr-caption-container" style="margin-left: auto; margin-right: auto; text-align: center;"><tbody>
<tr><td style="text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjIHuNxd9EYh9EjVlHY0XpqEiQHqLaH0Ig1k-mEZgKP5CnGhxH4LFqfYNF_KPaRXkzpj8Im85rzRpaokAaDO-SZq_bigiSgjM3-38Hrr0FjLfESXge1Wt4REr8ZuSL8mY0r2tQTgJ0UH_Q/s1600/IMG_0127%255B1%255D.JPG" imageanchor="1" style="margin-left: auto; margin-right: auto;"><img border="0" height="478" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjIHuNxd9EYh9EjVlHY0XpqEiQHqLaH0Ig1k-mEZgKP5CnGhxH4LFqfYNF_KPaRXkzpj8Im85rzRpaokAaDO-SZq_bigiSgjM3-38Hrr0FjLfESXge1Wt4REr8ZuSL8mY0r2tQTgJ0UH_Q/s640/IMG_0127%255B1%255D.JPG" width="640" /></a></td></tr>
<tr><td class="tr-caption" style="text-align: center;">Nexys2 board bottom left, logic analyzer above and breakout board attached to right</td></tr>
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It has a clock running at 50MHz and is field programmable by USB from the Digilent-provided Adept software on a PC, but could be programmed by the standard JTAG method too.<br />
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It hosts a flash ROM which contains the programming, loaded whenever the board is powered on or reset.<br />
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The board has features which are used for debugging convenience, such as eight switches, four push buttons, eight LEDs and four 7-segment LCD digits, but which will not be active in the final machine. There is support for a VGA interface which is not used. The board also provides more than 50 I/O pins from the FPGA, in eight digilent style "PMOD" connectors and in the 50 pin expansion connector. I use these for logic analyzer debugging but also for connections to other hardware, as will be outlined below.<br />
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16MB of flash memory is on board, plus 16MB of fast RAM, both of which were planned to be used in the 1130 project. The flash could hold seven virtual disk cartridges, any one of which could have been mounted in the emulated disk drive on the project. However, timing issues and complexity led to use of separate flash rather than the onboard flash, because of the sharing of the IO pins between RAM and flash that make it impossible to fully overlap their operation. The RAM is used to implement the 32K of 16 bit words in the largest 1130 configuration (plus the 2 parity bits per word).<br />
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A PS2 port is provided on the board and used to connect a PC keyboard to stand in place of the 1130s console keyboard. Later in the project I hope to put in a more accurate keyboard replica that provides just the signals which are emitted by the 1130 hardware itself, not PS2 keyboard scan codes. All the scan codes are converted by emulation logic to appear to be the micro-switches on the real keyboard of an 1130, thus the adapter logic from the 1130 is unmodified.<br />
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The USB link provided on the board provides a high speed and low speed transfer mode embodied in the Cypress chip on the board - up to 480MB/s transfer rate as a stream connection as well as emulating a PC extended parallel port (EPP) for low speed transfers. This is used to connect to software running on a PC, written in Python, to link the peripheral emulators on the board with external files and simulated lights and buttons of the I/O device. The current emulation planned includes 1132 printer, 1442 card reader/punch, 2501 card reader, 1627 plotter, console printer (typewriter) output, and a means to preload core memory (board RAM) and virtual disk cartridges (board flash). <br />
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External hardware I have built provides the console lights, switches, and buttons. The 1130 has more than 100 incandescent lights in a panel that indicates the value of system registers, conditions, the current T and I cycle and other status of the machine.It has several lighted buttons and button switches that sit alongside the console keyboard keys. There is a row of 16 toggle switches that sit on the front of the console printer. Six toggle switches are normally hidden and used by the maintenance engineer (the CE switches). The panel of lights sits on a pedestal above the console printer, which is a modified Selectric typewriter. The panel is built using LEDs rather than incandescent lights, built to appear as similar as possible to the real machine. It has a rotary dial switch on the right of the panel lights which is fully implemented and has an emergency pull switch on the left which I plan to build as a nonfunctional knob. The LEDs are controlled by boards I built using a chain of MAX7219 controller chips which are connected over a high speed serial link to the Nexys2 board.<br />
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Another high speed serial link, using the SPI protocol, links to a MCP23S17 chip that multiplexes the 16 toggle switches on the front of the console printer over the four wires of an SPI link. A third high speed serial link, using the I2C protocol, connects to two MCP23017 chips used to multiplex all the other buttons, switches and the virtual disk cartridge number, using only two wires.<br />
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All buttons and switches are debounced with MC14490 debounce chips before multiplexing and conveyance onto the Nexys2 board, just because it seemed simpler to do this at the time.<br />
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The Nexys2 operates at 3.3V but some of the chips, for example the MAX7219, require 5V signals (TTL levels), thus level shifters are placed at appropriate points on my boards - the MCP23x17 chips operate at 3.3V while the others run at 5V. 74HC4050 and 74HCT00 chips are used for the level shifting.<br />
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The console printer is essentially the 1053 console of the S/360 line, a Selectric modified by the addition of solenoids and microswitches to convert the purely mechanical Selectric typewriter to a device that can print data transferred from a computer. The Selectric is a very complex bit of machinery, requiring many solenoids and very, very precise timing of activation to avoid jamming the mechanism. Microswitches communicate the rotary position of various mechanisms as they operate to print, shift, tab, return the carriage, space and other tasks of the typewriter, controlling the timing of solenoids and used to interlock some operations that cannot overlap others. The adapter logic in the 1130 contains everything needed to interact with the switches and solenoids, if one could only find a 1053 or the IO Selectric or 2741 devices that are very similar.<br />
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It is one of the goals of this project to implement a Selectric as the console output printer. I have acquired a Selectric and a pile of solenoids, but also recently bought an IBM Electronic 50 which was a hybrid machine combining the Selectric mechanism with some electronics for limited editing and composition. it has the solenoids and switches already installed, thus should be fairly easy to interface as a console printer. I am waiting to receive scanned diagrams and documentation on the E50 from someone I came to meet on the GolfBallTypewriter group that has members interested in Selectrics and related machines - Dave Handyman (not sure if the surname is a nom de plume or his real world name) is a former CE who has quite a few documents and tools that he shares with the group.<br />
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I acquired a paper tape reader device which I intend to interface to the Nexys2 board to perform just like the 1130 paper tape reader. I have not found a suitable PT punch but did buy the punch block assembly for a Teletype, the physical part that punches the holes themselves, which I can connect to solenoids and build along with a sprocket drive to produce a paper tape punch that interfaces right to the 1130. No emulation will be necessary on either of these peripherals, just as no emulation is needed for the console printer.<br />
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Line printer support will be emulated, with code in the FPGA producing the signals and timing that woudl be seen if a real 1132 and/or 1403 where hooked to the 1130 adapter circuits. I have modeled the rotation of the print disc wheel and the timing and operation of the carriage and brushes, thus it should produce lines of output at the same speed as an actual 1132 without modification to the 1130 adapter logic. The 1403 is intended to be modeled, but i do not have full documentation of the printer adapter for that device yet, thus it is conditional.<br />
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Card reader and punch support is also emulated, with code in the FPGA modeling the physical mechanism, timing and behavior of both the 1442 and the 2501 devices. It is quite accurate to the timing of the real devices, with virtual card images transferred from the PC to a FIFO in the FPGA with all 12 holes state for all 80 columns. This means the cards coming in over the USB link with the hgih speed streaming mode are in Hollerith mode, boot card mode, binary mode, or any other mode that exists on the 1130. They are only converted to and from ASCII in the PC, the adapter logic remains unmodified.<br />
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The disk drive emulation is faithful to the timing and behavior of the single drive installed in most 1130 systems. I model the rotation of the drive, generate index and other pulses, generate and check the four parity bits, model the zeroes and sync word and all the other signals that are seen by the adapter, at the actual timing experienced on a real disk drive. This means that the programs will experience the same times to seek, read, write and even down to the same rotational delay waiting for a sector from one IO to the next.<br />
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If a real card reader can be acquired at a reasonable price, a future stage of this project would interface that reader to appear as a 1442 or 2501 to allow use of real cards. I have a Wright manual keypunch device and a few thousand blank cards, just in case.<br />
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I may, in later stages, acquire a DEC RK-05 drive or similar cartridge disk drive as several firms licensed and produced virtually the same drive as the 1130. I own two cartridges for RK-05, for use if a drive can be found at reasonable price and modified to interface fully with the unmodified 1130 adapter.<br />
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Physically, I intend to construct the recreation 1130 as a tabletop unit, with the slanted formica top of the real 1130, the Selectric mechanism, keyboard, operator light panel and other gear at full size and as accurate as possible, but not build the remainder of the cabinet down to the floor as that would be almost totally empty wasted space in this implementation.<br />
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While not a standard peripheral used with the 1130, magnetic tape is a contemporaneous technology which I might interface to the machine, as I have a tape drive from an IBM p-series system on hand. I would need to invent the adapter, simplifying aspects of tape operation to bring it within the capabilities of the 1130 IO approach, as well as writing a device driver for DMS2, but that would be an interesting project after the system is fully operating.<br />
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My most recent acquisition (through Craigslist) is an HP Designjet 750C plotter, a monster that produces 36" wide printed output of both plots and pictures. I will use that as the plotter output for the 1130, generating plots from programs I write or copy from others. Since it also accepts sheet media, I have some 13 x 16 paper that I can use for smaller output. The designjet accepts HP/GL commands, which are produced by the interface unit built by Richard Stofer. That consists of an mbed microcontroller device that links to the fpga, converting the simple plotter operations from the 1130 into HP/GL and sending that over ethernet to a printer. He used it with a laser printer that includes HP/GL support, but I will point the unit to the Designjet 750C for added realism. Unfortunately, this monster unit will not look like the small plotter, which IBM OEMed from CalComp and sold as the 1627 peripheral for 1130 systems.<br />
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Another aspiration for a later stage is to record the sounds of a real 1130, separate out the sounds of the basic fans/hum, the disk drive seek sound, line printer sound, card reader and card punch sounds, etc, so these can be mixed and output on a PC speaker at appropriate times to further bolster the experiential fidelity of my recreated 1130.Carl Claunchhttp://www.blogger.com/profile/00359841432891565909noreply@blogger.com0tag:blogger.com,1999:blog-7951573759848963517.post-71897518280609625712013-12-01T04:30:00.000-08:002012-12-27T04:30:45.118-08:00Watch out for those special slowed down versions of machinesAt least twice I have been bitten by studying documentation to understand the logic or the timing of a machine, when I didn't notice that the instance I was studying had been artificially slowed to produce a low end, low price point model.<br />
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The first time was when the T clock logic of my machine was first ready for debugging after implementing the machine according to the full set of ALDs online at bitsavers.org, from the machine named 1130C. The T clock steps through 280 nanosecond cycles from T0 to T7, which encompasses one storage access cycle of the 2.2 microsecond core memory (these timings are for the fastest of the 1130 models). Various conditions block or cause the T clock to advance, among them "extra" T7 cycles which are required in the 1130 when certain operations can't be completed by the end of the first T7 cycle.<br />
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Addition in an 1130 occurs iteratively, with a bitwise binary addition in a T cycle producing the carry bits from each bit as a new addend in the D register to be applied for another round of addition. Only when the D register is all zeroes, meaning that all carry values have rippled through the result, is the arithmetic operation complete. This is marked by dropping the signal "arithctl" when D is all zero. If we are at T7 and arithctl is still on, then instead of advancing to T0 as normally would happen, the clock stays at T7 for at least another 280ns cycle.<br />
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The logic analyzer showed the T clock advancing cleanly each 280 ns from T0 up to T7, but it was always taking several extended T7 cycles. I assumed that the timing of some signals was off, not arriving in time to allow the T clock to advance to T0, thus began carefully reviewing the timing of all relevant signals. I couldn't see any issue, yet the T clock was delayed in advancing to T0 for every storage access cycle.<br />
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Finally it dawned on me, while walking through the ALD pages related to the T clock, that this behavior I was seeing on the recreated 1130 was the intended behavior of the circuits. The ALD had some FFs forming a counter that would count away some 280 ns cycles before it triggered the advance of T clock to T0.<br />
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With the philosophy of this recreation stressing as near exact reproduction of the logic circuits gate by gate as possible, I had coded page after page of ALD diagrams into VHDL but hadn't analyzed the purpose and intent of every gate or signal. I found that I had implemented this delay counter because it was there on page KM212, labeled "T7 Extend". To my surprise, it turns out that machine 1130C is a model 4, a special model that runs slower than the others. While its brothers with the 3.6 microsecond core storage run with T0 following directly after T7, the model 4 runs at an speed of 4.5 microseconds because of the extra T7 cycles that are tossed in to waste 900 nanoseconds at the end of every storage cycle. This was the reason for the delay counter and the reason that my recreation was experiencing extra T7 cycles. Had I realized this up front, I would not have coded in the delay counter nor had any wasted T7 cycles to debug. I modified the VHDL to turn this into a full speed machine, no intentional wasted T7 cycles.<br />
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The second incident where an artificially slowed model caused me to spend hours of unnecessary time was with the emulation of the 1132 printer. I had to understand the mechanism inside if I were going to provide accurate timing simulation of the printer and reproduce its behavior faithfully. I had to emit various pulses and signals from the emulated printer to the device adapter logic of the 1130, and these had to be at the right time if the adapter logic were to work as intended and any printing would run at the same lines per minute as a real 1132.<br />
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This printer was built for the 1130 by taking the printing engine of the pre-computer punched card accounting machine, model 407, and wrapping a minimum of electronics around it for use by 1130. This kept costs down by leveraging and perhaps recycling mechanisms from the base of 407 machines that were being replaced by electronic computers.<br />
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At its heart is a cylinder of type rotating in front of the paper, hammers pushing the paper onto the wheel when the intended letter was rotated into position. To decide when to strike a hammer, the machine had a 'print disc' on the end of the cylinder that was read by photocells to emit timing pulses and the seven bit value of the letter that was just rotating into print position next. I had several timing diagrams of the printer which were guiding my emulation - I would put in delay counters to wait for timings based on the documentation, or emit pulses of durations given by the documentation at appropriate points. The emulator hardware sets a print disc rotating at the speed of the 1132, bringing each of the 48 characters than can be printed in the actual order they are arranged around the cylinder of a physical 1132 printer. Based on the rotation speed, the wheel moved from character position to the next position every 11+ milliseconds.<br />
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The way this was driven by programs was pretty byzantine. The printer would interrupt the 1130 once every 11+ milliseconds, which the program would respond to with an XIO Read to get the seven bit value of the upcoming character. The program then looked at the line it was printing, setting a 1 bit for every hammer position of the 120 columns that matched this one character. The bits were set in a fixed location, the scan buffer, which the 1132 printer would fetch with cycle stealing when it was time to actually print the character, firing the hammers to strike those columns where this letter was wanted. The program would then wait for the next interrupt, print the positions that contained the next character, and do this up to 48 times until all the character values in the print line had been printed.<br />
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One of the diagrams showed the interval between the pulses that caused the interrupt and the actual printing to be 22+ milliseconds. That implied that it would take two full rotations of the cylinder to print a line if it had all 48 character values in it. However, the rated speed of the printer, both for numeric only and general print lines, could never be attained in this case. Even all-numeric lines would involve more than one turn of the cylinder, because the type for the digits were adjacent on the cylinder. If the cylinder rotates to the next digit in 11 ms but it takes 22 ms to read and react, extra rotation was inevitable.<br />
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I was quite concerned about this because of the dichotomy between rated speed and the timing diagrams. I spend hours trying to imagine schemes that would still allow a printed line to complete with only one rotation of the cylinder.<br />
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In a chance conversation with a docent at the Computer History Museum, in front of one of their 1130 machines on display, I was relaying the problem I hit with the model 4 and its slow-down by wasted cycles. The docent who had quite a bit of 1130 experience in his earlier days mentioned several other places where IBM created slowed down, entry level priced models through delays like this. He happened to mention that slowed down models of the 1132 were offered - the light bulb went on! I had timing diagrams from a slowed down 1132, once again these were from the 1130C machine ALDs. I looked at the timing diagrams for the 1130B machine on bitsavers, whose ALDs were incomplete but did contain the timing diagrams, which gave me a correct timing diagram. Only 11+ ms from the pulse causing the interrupt until printing, not 22. The longer time was a delay built into the slowed printer model. That model would print at half the lines per minute of its normal breathren. Mystery solved and emulation design was easy from that point forward.<br />
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However, throughout the construction of this replica, I had to carefully check for missing logic or changes based on such machine specific details. Not solely slowdowns for entry level models, but also address lines and register bits eliminated if a machine had less core than the largest configurations - a 32KW machine needed 15 address lines but an 8KW model would have two of those lines and all the related flip flops eliminated to reduce costs. I had to think through every ALD page that touched on memory addresses to be sure that I had all the logic needed for full 32KW implementation.<br />
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As well, if a machine did not have a card reader installed, for example, then cost would be saved by deleting all the signals and circuits related to that device. Interrupt and cycle stealing logic in particular varied quite a bit based on such configuration issues. By comparing the 1130 B and C ALDs from bitsavers and portions of the ALD from the 1130 being restored at the National Museum of Computing, I identified and included logic related to several such options. Sometimes the timing of other signals needs to be delayed or generated earlier to suit a device - the Storage Access Channel (SAC) and the attached multiplexor channel (the 360 mux channel was leveraged by the 1130 to attach the 1403 printer, 2260 graphics stations, 2310 and 2311 disk drives and other such peripherals). I will need a full set of ALD pages for the SAC in order to properly support it - the bitsavers machines do not contain SAC support.Carl Claunchhttp://www.blogger.com/profile/00359841432891565909noreply@blogger.com0tag:blogger.com,1999:blog-7951573759848963517.post-22811152158165009362013-11-30T17:38:00.000-08:002013-01-09T12:18:17.792-08:00Abandoning plan to use onboard flash as a disk driveThe original plan for this system was to make use of the onboard flash on the Nexys2 board, whose 128MB capacity seemed to offer room to place seven virtual disk cartridges and access them from the disk emulation hardware as needed. The speed of the 1130 disk is slow, with 28 microseconds between each word as the data is streaming in or out of the heads, which would appear at first glance to easily allow for use of flash to read or write the word as needed. The flash has an effective write time of 13.6 microseconds per word, but that is at best case which would require building and writing 32B buffers not individual words, with some kind of FIFO buffer between disk emulation and the flash access module.<br />
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A complication comes from the implementation on the Nexys2 board, where the address, data and most control lines are shared between RAM and flash. Only one is accessed at any given time, with RAM the clear priority to ensure the 1130 operates correctly and meets its realistic timing objective. Thus, access to flash would have to fit 'in between' the 1130 CPU and cycle steal accesses. The initial concept was to only allow flash access at phase A of a T7/X7 cycle, finishing up any flash access use of the signal lines before the 1130 itself begins RAM access.<br />
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The complexity of overlapping all this, with operations such as a write of a 32byte block taking well over 200 microseconds to complete, then needing to asynchronously empty a FIFO on that long timescale. Plus, the challenges of error recovery are thorny since the disk emulation module and 1130 program itself will have moved well past the IO by the time the last part of a sector is written. Any problem is detected long after we could have presented some meaningful status to the software running in the 1130.<br />
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At this point, I suspect that any flash or disk drive used to emulate the disk drive will be hung off a fast serial link of some sort, eliminating the shared signals that ultimately forced me to drop use of the onboard flash. More later as I redesign and implement a replacement mechanism.<br />
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It is also possible that I will figure out a method that safely exploits the onboard flash, which would have been the most natural approach, most efficient in space and energy use. .Carl Claunchhttp://www.blogger.com/profile/00359841432891565909noreply@blogger.com0tag:blogger.com,1999:blog-7951573759848963517.post-48370493766337682422013-11-29T21:10:00.000-08:002013-01-01T21:11:09.248-08:00Building the console hardware prototypesHere is the wiring for half of the console lights panel for the 1130 replica - these are the lights that display the contents of IAR, SAR, SBR, ACC, EXT and AFR registers, bits 0 to 15.<br />
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<tr><td style="text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEgVdgzCoyZsYFxu83Oq2IYV-DLUO5wGrI7MccnOpRdtkCgK6vJqr6OGEr4aGsfdArQKz7hy8TgYoUXqCKVlHs7lEGD10canQjRnUhM4JnMEMexea23VjzdZilz7MW2emoapWhiL1NdqIhU/s1600/IMG_0128%5B2%5D.JPG" imageanchor="1" style="margin-left: auto; margin-right: auto;"><img border="0" height="239" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEgVdgzCoyZsYFxu83Oq2IYV-DLUO5wGrI7MccnOpRdtkCgK6vJqr6OGEr4aGsfdArQKz7hy8TgYoUXqCKVlHs7lEGD10canQjRnUhM4JnMEMexea23VjzdZilz7MW2emoapWhiL1NdqIhU/s320/IMG_0128%5B2%5D.JPG" width="320" /></a></td></tr>
<tr><td class="tr-caption" style="text-align: center;">Wiring of 96 LEDs for the left side of console light display</td></tr>
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These are placed in 1:1 scale to an IBM 1130 display - the board you see is 4" by 10", the left side of the 1130 panel lights encompass a 5" by 10" space, adding in the right side produces the 20" x 5" black display that lights to indicate the contents or status of key parts of the machine. This board will sit inside the display panel box, with 1/2" clearance to the top and bottom, fronted by a smoked plexiglas plate that will recreate the lettering and cutout numerals that are lit by the LEDs in each position. </div>
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<tr><td style="text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEgGWOOA2ZP3_wcxIco4_fCneXfOgRheu-R42yJE5i2iFqBle1XQYG3AHurOP2ZsDyas9ItbPhicdomFsIGXZ9AZyIjsFpJbhd2xvrTB_tTUdnxGAmwL4lHNuHfz15VGtXYp5mntENqQ8hA/s1600/IMG_0129%5B1%5D.JPG" imageanchor="1" style="margin-left: auto; margin-right: auto;"><img border="0" height="239" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEgGWOOA2ZP3_wcxIco4_fCneXfOgRheu-R42yJE5i2iFqBle1XQYG3AHurOP2ZsDyas9ItbPhicdomFsIGXZ9AZyIjsFpJbhd2xvrTB_tTUdnxGAmwL4lHNuHfz15VGtXYp5mntENqQ8hA/s320/IMG_0129%5B1%5D.JPG" width="320" /></a></td></tr>
<tr><td class="tr-caption" style="text-align: center;">Left side of light panel - contents of six registers</td></tr>
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The six registers, from top to bottom, are the Instruction Address, Storage Address, Storage Buffer, Arithmetic Factor, Accumulator, and Accumulator Extension Registers, each 16 bits wide.</div>
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<tr><td style="text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEi8WtpVqMU74BvHUZILJayyptmwSvJyJ4o519oUMYBl-g5Wm28P-7fu1XPqfzfuiwWgI3ttJ1rGNHPz_pKIyraiwHCklSmnHCq8aYCzCj7JLY2LvhxzoVCw4DXrWR_95VePe1bZn9F7Ci8/s1600/IMG_0101%5B1%5D.JPG" imageanchor="1" style="margin-left: auto; margin-right: auto;"><img border="0" height="476" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEi8WtpVqMU74BvHUZILJayyptmwSvJyJ4o519oUMYBl-g5Wm28P-7fu1XPqfzfuiwWgI3ttJ1rGNHPz_pKIyraiwHCklSmnHCq8aYCzCj7JLY2LvhxzoVCw4DXrWR_95VePe1bZn9F7Ci8/s640/IMG_0101%5B1%5D.JPG" width="640" /></a></td></tr>
<tr><td class="tr-caption" style="text-align: center;">IBM 1130 at National Museum of Computing, Milton Keynes, England, UK</td></tr>
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Our light panel represents the left half of the black rectangle you can see to the right of the red 'emergency pull" switch. </div>
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<tr><td style="text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEgDwMVHoo_gpDJ3f4B-H9myiYwqwYrZdkMigKIUcaptCCSE0m2zrYPc1MMcOwFbztwVp8TmqjlMCST5TWd-ZyYXZIjWfqSHXPiWFbSWj5PKdxA1YpIRbF3glbtOrkA6ILxq9X6VCAM2NoY/s1600/IMG_0130%5B1%5D.JPG" imageanchor="1" style="margin-left: auto; margin-right: auto;"><img border="0" height="320" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEgDwMVHoo_gpDJ3f4B-H9myiYwqwYrZdkMigKIUcaptCCSE0m2zrYPc1MMcOwFbztwVp8TmqjlMCST5TWd-ZyYXZIjWfqSHXPiWFbSWj5PKdxA1YpIRbF3glbtOrkA6ILxq9X6VCAM2NoY/s320/IMG_0130%5B1%5D.JPG" width="239" /></a></td></tr>
<tr><td class="tr-caption" style="text-align: center;">LED driver boards</td></tr>
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<span style="font-size: 13px;">Prototype boards implementing a chain of three MAX7219 chips that will drive 192 LEDs based on data sent over a three wire serial protocol link from the recreated 1130 FPGA board. This board operates at 5V and has a level shifting 74HCT00 chip to permit it to operate with signals from the FPGA which are based on 3.3V logic levels. </span><br />
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<tr><td style="text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEg32ZWtohyphenhyphengEkX2Sc42voCoKJKW4Z0jEnrMvBdmlJ2CaLJhJW-Jq8jfEdbKDblUp4PBJUXprhx18nBKL-qsyHU-XVRNMFsMjXi_Mgo4FQ_7rtsLQLHplyzsuCfqhI78McrahmUgRh46108/s1600/IMG_0131%5B1%5D.JPG" imageanchor="1" style="margin-left: auto; margin-right: auto;"><img border="0" height="320" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEg32ZWtohyphenhyphengEkX2Sc42voCoKJKW4Z0jEnrMvBdmlJ2CaLJhJW-Jq8jfEdbKDblUp4PBJUXprhx18nBKL-qsyHU-XVRNMFsMjXi_Mgo4FQ_7rtsLQLHplyzsuCfqhI78McrahmUgRh46108/s320/IMG_0131%5B1%5D.JPG" width="239" /></a></td></tr>
<tr><td class="tr-caption" style="text-align: center;">Switch/Button input multiplexor board</td></tr>
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The board shown above will take 32 button or switch contacts and multiplex them over a two wire I2C serial bus to the FPGA 1130 machine. The board operates at 3.3V to interface with the FPGA board, but has level shifting chips to allow 5V logic levels for inputs. It is used with the debouncer board below. The buttons, toggle switches and rotary switches of the 1130 console, except for the 16 toggle switches that are mounted on the console printer faceplate, are routed through this concentrator and into the hardware on the FPGA board. Uses an MCP23017 to multiplex signals and several 74HC4050 level shifter buffers which tolerate 5V inputs and produce legal 3.3V outputs.<br />
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<tr><td style="text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEizalUIs6xS9-K_lbBuBzIstvirvW-Jsb-a67pG1sj537dpwlFgvkg-ulLyU12Um4Qjc2l7i0p8zzfS_iATU0rSWt6YvNhMyUlAEQ858vAefd3ks26fUg9ZJXCU4OOpfHF16rz2hOK2_Gs/s1600/IMG_0132%5B1%5D.JPG" imageanchor="1" style="margin-left: auto; margin-right: auto;"><img border="0" height="320" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEizalUIs6xS9-K_lbBuBzIstvirvW-Jsb-a67pG1sj537dpwlFgvkg-ulLyU12Um4Qjc2l7i0p8zzfS_iATU0rSWt6YvNhMyUlAEQ858vAefd3ks26fUg9ZJXCU4OOpfHF16rz2hOK2_Gs/s320/IMG_0132%5B1%5D.JPG" width="239" /></a></td></tr>
<tr><td class="tr-caption" style="text-align: center;">Input debouncer board</td></tr>
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This debouncer will remove any bouncing of the state of the buttons as they are operated, where contacts produce a short term blizzard of on and off conditions as the physical switch is pressed or released, but the intent is to record just the selected final condition - 1 or 0 - which the switch will settle down to deliver steadily a few milliseconds after it is operated. The debouncer eliminates those glitchy short term effects and passes through only the intended change, on to off or off to on. This board as built implements debouncers for 24 switches/buttons, more chips are added as more buttons are required. Uses MC14490 debouncer chips which operate on 5V, producing the signals that are shifted down to 3.3V signals by the buffers on the concentrator board above.<br />
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The 16 toggle switches, called the Console Entry Switches, are separately multiplexed by an MCP23S17 chip which is very similar to the MCP23017 but uses the SPI protocol, a four wire serial link, rather than the I2C protocol of the other chip. Debouncing is currently done in the FPGA hardware but will be handled by MC14490 chips in the next version of the board (not pictured here).<br />
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Together, these boards allow 240 input and output devices (LEDs, buttons, and switches) to be connected using only 9 wires into the FPGA.Carl Claunchhttp://www.blogger.com/profile/00359841432891565909noreply@blogger.com0tag:blogger.com,1999:blog-7951573759848963517.post-6384577448752294502013-11-23T15:21:00.000-08:002013-01-23T14:24:10.309-08:00Interfacing the console printer mechanismThe Selectric typewriter is a purely mechanical device, using an electric motor solely as a power source to spin rods and move levers. it could as easily be powered by a steam engine or foot pedals. Thus, when IBM adapted it as a console printer (the 1053 used with the 1130 and 360 computers, the 2741 terminal used for timesharing and the I/O Selectric used to interface to minicomputers), it required a complicated set of additional mechanical components and some very careful timing and interlocking.<br />
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<tr><td style="text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEiqNLplz3U1VcJ1gEZUnLxyrbKeEbAOM3_DJdAaa91vQtEHRegY9RCYX-6iRRU66iA_gsm1VN6z1n7SeCtliQYDRJMFfrQaYl9q44DllAYYKNenX_DlezUbNOprp0_9qQLoiqnwwVDynBM/s1600/IMG_0134.JPG" imageanchor="1" style="margin-left: auto; margin-right: auto;"><img border="0" height="298" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEiqNLplz3U1VcJ1gEZUnLxyrbKeEbAOM3_DJdAaa91vQtEHRegY9RCYX-6iRRU66iA_gsm1VN6z1n7SeCtliQYDRJMFfrQaYl9q44DllAYYKNenX_DlezUbNOprp0_9qQLoiqnwwVDynBM/s400/IMG_0134.JPG" width="400" /></a></td></tr>
<tr><td class="tr-caption" style="text-align: center;">IBM Selectric with mechanical key linkage to print mechanism</td></tr>
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The keys on an ordinary Selectric move down, causing a lever to selectively pull on several rods inside the machine that select the typeball position. These are the tilt and rotate levers, where the lever for an individual key has a hook corresponding to the tilt and rotate rods it should activate, no hook for the others.Thus, movement of a key downward activates these rods. The rods are connected to a clever mechanism that converts a rotate code into the proper amount of movement of a tape that turns the golfball typehead. In the same way, the tilt lever selected swivels the ball up or down the desired swing to bring its row of characters into position. A particular letter might be accessed by Tilt 1 and Rotate 2, for example, which the key lever hook on when the typist pushes the key down. The key lever also hooks a rod that triggers one rotation of the basic print cycle rod, which makes the golf ball spin to the right position, slam forward into the ribbon, and then allows the 'carriage' position to move forward.<br />
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The 1130 makes use of its console printer by sending the Tilt and Rotate codes, the adapter causes these to pull on solenoids at the right time. A solenoid is an electromagnet which pulls in on a metal cylinder - the other end of the cylinder is attached to some lever in a mechanism. Current into the solenoid produces a mechanical movement. Each of the several tilt and rotate rods has its own solenoid, and the basic print cycle lever has a solenoid. The adapter activates the tile/rotate solenoids and then fires the print cycle.<br />
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If another key were pressed while the selectric was still doing the prior character, or a key was typed while some activity like a carriage return were occuring, the mechanism would jam. On the physical Selectric, mechanical means are used to lock out keystrokes until they are safe. Shifting the typewriter to upper case is going to cause a hard jam if the unit is already in upper case condition, thus these kinds of conditions must be avoided too. The way this gets handled on the 1130 is by inserting microswitches to report such conditions, and by having some microswitches activate to report where the mechanism currently is within the rotation of a power rod, such as the one that powers the basic print cycle. The adapter takes those indications from the switches plus uses a timer to delay the minimum time needed for the print cycle to complete, all to allow safe printing. Tabbing, backspacing, indexing down a line, shifting to upper/lower case, returning the carriage and other actions are handled by different power rods triggered by their own levers - yanked by appropriate keys on a typewriter and yanked by solenoids on the console printer. The 1130 adapter sends signals to solenoids installed for all these functions as well.<br />
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<tr><td class="tr-caption" style="text-align: center;">Microswitches providing feedback from E50 Selectric</td></tr>
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The mechanical keyboard is not used on the 1053 console printer, with the solenoids accomplishing the hooking and pulling of rods and levers that the key movement would accomplish on a plain typewriter. The 1053 printer corresponds to the IBM Selectric 2 - the typeball used on the 1130 computer is based on that version of the typewriter.<br />
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I own a Selectric 2 that I intended to modify by installing my own solenoids and microswitches. The solenoids are already purchased, but not the switches as the detailed plan for placement was still to be done.<br />
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<tr><td class="tr-caption" style="text-align: center;">Solenoids I intended to use to convert Selectric 2 into a console printer</td></tr>
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I found an IBM Electronic 50 on ebay - this is a much newer Selectric based system that has solenoids and switches already installed, since it has decoupled the keyboard from the printing mechanism.<br />
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<tr><td class="tr-caption" style="text-align: center;">Electronic 50 has keys separated from print mechanism</td></tr>
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Inside the E50 is a circuit board that implements logic to store keystrokes, allow editing, and then type the buffered document separately. This is a much easier basis for producing an 1130 console printer, because the mechanical connections and wiring are already in place.<br />
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<tr><td style="text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEg9tEKwQDB5U66RTDccazjOinqSYNLygiJepLWhA0DlfXVVjo6dLkQpLjXtyyyISe_tUzXm3-oYmsGpbQucqeFv3olxU35NeIrVki-XmVhuD0OK7uKytwkDy-9Vz6_rWQRMs672r11L61I/s1600/IMG_0133.JPG" imageanchor="1" style="margin-left: auto; margin-right: auto;"><img border="0" height="298" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEg9tEKwQDB5U66RTDccazjOinqSYNLygiJepLWhA0DlfXVVjo6dLkQpLjXtyyyISe_tUzXm3-oYmsGpbQucqeFv3olxU35NeIrVki-XmVhuD0OK7uKytwkDy-9Vz6_rWQRMs672r11L61I/s400/IMG_0133.JPG" width="400" /></a></td></tr>
<tr><td class="tr-caption" style="text-align: center;">Seolenoids and circuit board in Electronic 50 Selectric</td></tr>
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However, two issues remain that must be overcome. First, the typeball used on the E50 is incompatible with the Selectric 2, featuring more character positions to cite one difference. Thus a typeball from an 1130 won't work properly. As I hoped to find an APL typeball and run 1130 APL on my replica, this will be a barrier. Second, the microswitches and means of reporting the rotary position during operation of cycles, such as a basic print cycle, are different. Optical pulses are sampled by the circuit board in the E50, rather than microswitch contacts being activated. My interfacing my require some custom microswitches or an adapter circuit to convert to the kind of feedback signal expected by the 1130 console printer adapter logic, which believes it is connected to a 1053, not an E50. I may need to produce one or more custom typeballs or translate tilt/rotate codes on the fly in order to produce the intended printed characters from the E50 typeball.<br />
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The IBM solenoids operate at 48V, requiring me to design and build a circuit card taking 3.3V logic inputs and activating the solenoids with 48V at sufficient current to work properly. That is still in design, but I will build a prototype board shortly to begin testing the integration of the E50 into the 1130 system.<br />
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<br />Carl Claunchhttp://www.blogger.com/profile/00359841432891565909noreply@blogger.com0tag:blogger.com,1999:blog-7951573759848963517.post-3948921443228243252013-11-19T17:04:00.000-08:002013-01-19T08:00:45.053-08:00Testing the prototype of the console hw - part 1<div class="separator" style="clear: both; text-align: center;">
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In order to validate the design of the physical console that will provide the lights, buttons, switches, keyboard and printer of the IBM 1130, I put together prototypes and wired up a test to prove it out before finalizing construction plans.<br />
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The display light panels were formed using LEDs in the final pattern that will be illuminated behind a plexiglas panel in the pedestal unit that sits above the console printer on the IBM 1130. These were cabled to the display drivers, fanout logic, concentrators, switch debouncers and data links, which were attached to the FPGA 1130 and tested. Switches from scrap panels of IBM 3420 are used, along with toggle switches for the Console Entry Switch group temporarily mounted on a cardboard rectangle, and a rotary switch to be used for the Mode switch on the pedestal were wired in to test actual hardware components intended for the replica 1130.<br />
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The keyboard and console printer elements are not yet ready for testing, although temporary logic is provided to allow a PS/2 keyboard to be used for entry. The key layout is matched, but the keycap markings, shapes and colors are not the same as the 1130 and the feel is completely different. It will allow debugging and use of the system until the final keyboard mechanism is constructed. Similarly, emulation is provided for the IBM 1053 device used as the console printer, emitting ascii over the fpgalink to a PC which will display what is being 'typed' by the console device. These two emulated portions will be tested a bit later, followed by prototype testing of the final designs once my keyboard and printer hardware is ready.<br />
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<tr><td style="text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEigmBQCk9OtwrDOoUO0oKa5RMdGLrAtZtA-HPoliVIxeus_ug8WR7ZStdnpLZ7ckgEJzYs1jSr2bqRJkmHw6m9RwLmDN_KKVoHFpeq27ZhtmiJRdmFP2ToPLU-Fxk1LMTDp2yDg8tX64OI/s1600/IMG_0140.JPG" imageanchor="1" style="margin-left: auto; margin-right: auto;"><img border="0" height="298" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEigmBQCk9OtwrDOoUO0oKa5RMdGLrAtZtA-HPoliVIxeus_ug8WR7ZStdnpLZ7ckgEJzYs1jSr2bqRJkmHw6m9RwLmDN_KKVoHFpeq27ZhtmiJRdmFP2ToPLU-Fxk1LMTDp2yDg8tX64OI/s400/IMG_0140.JPG" width="400" /></a></td></tr>
<tr><td class="tr-caption" style="text-align: center;">Prototype of light panel being constructed</td></tr>
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<tr><td class="tr-caption" style="text-align: center;">1130 Pedestal Light Panel</td></tr>
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The buttons and lights near the keyboard will be similar to these, although mined from scrap 3420 tape drive and scrap buttons found on ebay. These are wired through the debouncer to the concentrator. </div>
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<tr><td style="text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEhGYXMckuAEgU5rWp4iuVkqpaKSx9Sf087ZJsJTIJCLDNBsyUufbnbs48WY908ahysUEpGhjnijEPkG_BcuHMmPfiGCVn7Q0umpW0Q-vRfCjeBXyAfNrvv_C3j12AfuJ4mAwttLPadDHHg/s1600/keyboard+and+switches+only.jpg" imageanchor="1" style="margin-left: auto; margin-right: auto;"><img border="0" height="122" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEhGYXMckuAEgU5rWp4iuVkqpaKSx9Sf087ZJsJTIJCLDNBsyUufbnbs48WY908ahysUEpGhjnijEPkG_BcuHMmPfiGCVn7Q0umpW0Q-vRfCjeBXyAfNrvv_C3j12AfuJ4mAwttLPadDHHg/s400/keyboard+and+switches+only.jpg" width="400" /></a></td></tr>
<tr><td class="tr-caption" style="text-align: center;">1130 Buttons and Lamps near the keyboard</td></tr>
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<tr><td style="text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEgDpRnbUKnk_6onngrVDChp6ETusyCioQx_Qhb4DvZRQC2eFdhISIcXJoJGBaAQxgrDeyLTFFg1b6pB3mdME8m8INxwzamrAjIApAY6fUJRzK0Y044xX_MwaI4lwreZ-bIHHjbLElfifsM/s1600/IMG_0141.JPG" imageanchor="1" style="margin-left: auto; margin-right: auto;"><img border="0" height="298" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEgDpRnbUKnk_6onngrVDChp6ETusyCioQx_Qhb4DvZRQC2eFdhISIcXJoJGBaAQxgrDeyLTFFg1b6pB3mdME8m8INxwzamrAjIApAY6fUJRzK0Y044xX_MwaI4lwreZ-bIHHjbLElfifsM/s400/IMG_0141.JPG" width="400" /></a></td></tr>
<tr><td class="tr-caption" style="text-align: center;">Scrap 3420 panel to provide buttons and lamps</td></tr>
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The keyboard itself is repurposed from the 029 Keypunch, and that would be the first choice if I can get my hands on a keypunch or the parts, otherwise I will need to come as close as possible.</div>
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<tr><td style="text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEgVm-ycGpKwqDP1pB22QGo0h_7qTyQVR9GrOF7BHRmkdSOM6U7nf-8IdSZhKOlpc9dLqdN0evPwIqetUVvc4bRxS353Ipc22YddllRiLxTpmKftfMY1Cl7ok4VaHk7cCPhlwZZdZRXZSUg/s1600/keyboard+only.jpg" imageanchor="1" style="margin-left: auto; margin-right: auto;"><img border="0" height="137" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEgVm-ycGpKwqDP1pB22QGo0h_7qTyQVR9GrOF7BHRmkdSOM6U7nf-8IdSZhKOlpc9dLqdN0evPwIqetUVvc4bRxS353Ipc22YddllRiLxTpmKftfMY1Cl7ok4VaHk7cCPhlwZZdZRXZSUg/s400/keyboard+only.jpg" width="400" /></a></td></tr>
<tr><td class="tr-caption" style="text-align: center;">Keyboard of the 1130 (or 029)</td></tr>
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The Console Entry Switches go through their own concentrator board, one I received from Richard Stofer, wired to some toggle switches bought on ebay. These are not an exact substitute for the 1130 switches but are very long toggle handles to permit mounting in a realistic setting in front of the console printer.</div>
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<tr><td style="text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEilgT3hqnu5VBTGKFOs1tcCpPjalCqoPSeNzSdhKaE-xCGc-eajmyYf8yI_lukArwXDDLSGT892DmH4iLWm6KPJjLOatKrabrCU7vZWSB0rYDR5muAEOxyt8QUodk4K1SoPtvuSO7bdZIQ/s1600/ces+only.jpg" imageanchor="1" style="margin-left: auto; margin-right: auto;"><img border="0" height="87" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEilgT3hqnu5VBTGKFOs1tcCpPjalCqoPSeNzSdhKaE-xCGc-eajmyYf8yI_lukArwXDDLSGT892DmH4iLWm6KPJjLOatKrabrCU7vZWSB0rYDR5muAEOxyt8QUodk4K1SoPtvuSO7bdZIQ/s400/ces+only.jpg" width="400" /></a></td></tr>
<tr><td class="tr-caption" style="text-align: center;">1130 Console Entry Switches</td></tr>
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<tr><td style="text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEhZnwgceqdfqGKrJlAgNGzTwMJM_qINtMDXKlRihE7PDF3X1Xa53OG-UI0FqrdbIvhZvbPavcQ9LpvTM31Agh6LXTRji1H-ck7q9Dxpx9HAkuyJWWwRfMNIPcfUlKYmI4a4-7Qd2t62ctM/s1600/IMG_0142.JPG" imageanchor="1" style="margin-left: auto; margin-right: auto;"><img border="0" height="298" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEhZnwgceqdfqGKrJlAgNGzTwMJM_qINtMDXKlRihE7PDF3X1Xa53OG-UI0FqrdbIvhZvbPavcQ9LpvTM31Agh6LXTRji1H-ck7q9Dxpx9HAkuyJWWwRfMNIPcfUlKYmI4a4-7Qd2t62ctM/s400/IMG_0142.JPG" width="400" /></a></td></tr>
<tr><td class="tr-caption" style="text-align: center;">My CES prototype with R. Stofer's board</td></tr>
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The Console Entry Switches work well, tested and used with the load and display modes of the machine.<br />
Once the switches are mounted in their more permanent location on the console printer faceplate, this will be fully usable.<br />
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The test setup with the console display lights hooked into the 1130 - not working properly initially, recoding along with testing to fine tune. Didn't put enough capacitors protecting the + power to the board, to avoid the impacts of all the current switching into and out of the LED array. This removed glitches to yield a much more reliable transfer to the MAX7219 chips. Found a few bad LEDs, some broken wires in the harness and a few unsoldered leads on my prototype board. Cleaned up and moved on to debugging the displayed state of the lights. There are still glitches occuring, thus more work needed on the prototype board, as well as some wiring issues remaining in the right hand board. Progress is steady, however, and it is only a matter of time before this is solid enough to consider the design final. At that point I will design a production printed circuit board and build it.</div>
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<tr><td style="text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEityKjZhdJujTLfxVhZC3Y5qGK__ebSuSKH0xeZlsYXtNr06EOoVEUNB_UGPYhtwFPcfYvGNaXIGnL1Wa9sNSfIGYRtaD-oJ5TijPngvkqL_vfNVAfmwH_xOLm88YffYdxOXhWGMd1H12Q/s1600/IMG_0145%5B1%5D.JPG" imageanchor="1" style="margin-left: auto; margin-right: auto;"><img border="0" height="298" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEityKjZhdJujTLfxVhZC3Y5qGK__ebSuSKH0xeZlsYXtNr06EOoVEUNB_UGPYhtwFPcfYvGNaXIGnL1Wa9sNSfIGYRtaD-oJ5TijPngvkqL_vfNVAfmwH_xOLm88YffYdxOXhWGMd1H12Q/s400/IMG_0145%5B1%5D.JPG" width="400" /></a></td></tr>
<tr><td class="tr-caption" style="text-align: center;">Testing the light display panel hardware</td></tr>
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The button and switch entry unit were debugged, then tested with the 3420 tape unit buttons hooked through the debouncer board to the multiplexor board, whose link worked well with the console link function inside the fpga. Work is now underway to design a final printed circuit board for the button/switch entry logic, merging the debouncer and multiplexor boards into one. This will be fabbed by an outside service and then components soldered on after I receive the board.<br />
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When the production version circuit boards are built, I will conduct a second round of testing/debugging of the completed system. </div>
Carl Claunchhttp://www.blogger.com/profile/00359841432891565909noreply@blogger.com0tag:blogger.com,1999:blog-7951573759848963517.post-8096437452361474002013-11-01T09:18:00.000-07:002013-01-10T09:19:14.191-08:00The Search For Authentic HardwareWith realism of the experience for a person using the 1130 replica as a key objective, it was important to recreate as much of the system as reasonable. That is one of the reasons to build a physical panel with the blinking lights at full size, as well as the rationale for using a Selectric typewriter mechanism for the console output. This entry describes the process of acquiring and/or building the appropriate parts of the machine.<br />
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Scrap parts for some mainframe systems are still plentiful in the used markets. IBM tape drive units are particularly active on Ebay at this time, where the operator panels include the same kind of switches and lights as are used on the 1130 - plastic rectangles in red, green, and blue for the pushbutton switches and rectangular plastic blocks in white, yellow, red and green for the lights. Some of the buttons are usable as purchased, for example the "Start" and "Reset" buttons, but others will need the wording altered to match the 1130.<br />
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On the console pedestal, alongside the blinking lights, are a rotary mode switch on the right and a red emergency pull switch on the left side. I found a suitable rotary electrical switch to actuate the mode switch, allowing selection of 'single step', 'single storage cycle', 'single instruction', 'normal', 'interrupt run', 'load' and 'display' modes. I am using a scrap part knob from a different IBM mainframe to make the mode switch appear as accurate as possible. The emergency pull switch is a problem, even though it will not be operational, because it is so iconic for IBM mainframes. These are apparently highly prized souvenirs and extremely difficult to find. At this point, I expect I will be building a replica to install on this 1130.<br />
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I have described the challenges of converting a Selectric typewriter mechanism to server as the operator console, but a brief discussion of some additional factors is warranted. I used Craigslist to pick up a Selectric II, bought solenoids from an electronics supply house, and then bought an Electronic 50 as that is potentially easier to convert. However, the mechanism is housed differently, since there is no typewriter keyboard on the 1053 console printer. I will modify or build a housing that matches the 1130, place it around the converted typing mechanism, and integrate the tabs/carriage indicator. I will need to add a rocker for tab set/release, as well as button switches for Tab, Space and Return. Finally, the front of the printer also features 16 white tipped, silver handled toggle switches called the Console Entry Switches. I bought large toggle switches with extended handles, but will need to convert the ends with white caps to match. Most likely, I will grind down the ends to a stub cylinder, then glue on a white plastic cap that I make with a 3D printer.<br />
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The keyboard is a mechanical device with the unique heavy feel of the 029 Keypunch whose mechanism it leverages and the unique key layout and key shapes. I am currently trying to buy a very similar keyboard on Ebay, which is photoelectric not mechanical but otherwise identical in appearance and layout because it was built as part of a keypunch system. The initial price was just too high for the realism it provides ($350 plus shipping), especially because I can't feel the action of the keyboard in advance and don't know if I can implement the interlocking and need for a reset key to release a 'jammed' situation. I sent emails to the seller offering a lesser amount, but the buyer has not deigned to reply, although it was relisted a few times and reduced to (a still too high price of) $299. After the last auction elapsed, I emailed one final offer of $200, probably way too much but I am still receiving deafening silence from the seller. Sometimes people have firm ideas of what they believe their goods are worth, in spite of continued market evidence to the contrary, and they become offended by any suggestion of a lower price, not even bothering to counteroffer.<br />
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The fallback is to create a keyboard using mechanical switches, some foam or other material to increase the keystroke resistance, and some method yet unknown to create the lockout (jam) condition. Another alternative is to separate the keyboard portion of the electronic 50 typewriter, which is already fitted with microswitches, and make use of some form of that as a mechanical keyboard. This would certainly provide the interlock and need for a solenoid to release 'jams', but requires custom keycaps and may be difficult to map exactly to the 1130 keyboard layout. More research will be needed.<br />
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The tabletop will be wood with white laminate, similar to the actual 1130 table, but not full height off the floor. Instead, it will look as if someone had used a chain saw to cut off the top of an 1130, leaving just six inches or so below the lowest edge of the tabletop. The metal portions will be copied, as these are all painted and can be replicated pretty well - pebble finish except for the plate atop the keyboard which is smooth - and in authentic colors.<br />
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I have access to real 1130 systems at the nearby Computer History Museum and also at a nearby private collector's home, allowing me to measure more accurately, test coloring and finishes, and test out the keyboard action. The CHM machine can't be touched, although I might be able to arrange permission using gloves, but the collector's machine is going to be fully accessible. I would like to check out the intensity and behavior of the lights on the pedestal console display, and to record the noises of the 1130, but neither of these machines are powered. There are two powered machines I might get access to for the light investigation and recording - one nearby at a second private collector's home and the other near London in the UK at the National Museum of Computing.<br />
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I am producing peripheral replicas as possible - paper tape, plotter, card and printer devices are all possibilities. Initially the plotter is handled by a clever unit built by Richard Stofer that converts the plotter instuctions of the 1130 adapter into HP-GL commands over TCP/IP, allowing it to drive any HP-GL compatible plotter or printer. If I buy a plotter that could be forced into a replica housing, I might be able to produce the 1130-like plotter, but at worst it will be used to link to a HP-GL compatible laser printer.<br />
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I have bought a paper tape reader mechanism on Ebay (it was how I came to meet one of the private collectors in the area) which I will fit into a replica housing to look like the 1130 peripheral. I bought the punch block for a teletype - the dies and fitted holes that are driven to punch holes in paper tape - which I only need to fit to solenoids and install with a sprocketed driving mechanism in order to build the paper tape punch. If this pans out, I will also need to buy some blank paper tape stock on ebay.<br />
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Punched Card equipment is in short supply, but I may be able to create some form of punched card input/output. There are occasional readers or punches appearing on ebay - right now there is a duplicator (both reading and punching plus the card transport capability) but the offered price at $495 is a bit high since there is no guarantee it is in working condition. I have a mechanical keypunch (Wright 2600) and a box of 2000 blank cards, both bought on ebay, thus I could move forward on the reader/punch if I choose.<br />
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Line printers are difficult to build as a replica, mostly due to the lack of continuous form paper supplies. and the fact that chain or wheel based printers have long been replaced by other mechanisms like laser printers, but the right basic mechanism might show up somewhere and trigger a subproject.<br />
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Disk IO on the 1130 uses the 2310 mechanism and the 2316 disk cartridge. Used cartridges are found on ebay periodically, but not the drive mechanism. However, several other makers built similar products, including DEC (RK-05 disk), Pertec, and CDC, any one of which could be pressed into service. The unique 'grunting' sound of the actuator might need to be reproduced, since the mechanisms for seeking and positioning are different on the compatible drives, but many options exist. First, I could put flash memory inside a disk cartridge along with zigbee or similar wireless, allowing the cartridge to be placed into a mock disk mechanism and accessed - playing some simulated disk sounds as it operates. I have bought an IBM 8" floppy drive mechanism as it seems to use a mechanism most directly derived from the 1130's disk, thus it might provide the right grunting sound. I could use a floppy itself as the disk cartridge, or just use that part of the mechanism for authentic sounds - more investigation and design work is needed.<br />
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Other peripherals such as the 2250 graphic workstation, optical mark reader and alternative readers and printers, are not in scope at this time.Carl Claunchhttp://www.blogger.com/profile/00359841432891565909noreply@blogger.com0tag:blogger.com,1999:blog-7951573759848963517.post-85216883935155869042013-10-31T21:19:00.000-07:002013-01-17T21:19:40.374-08:00Learning experiences and new toolsThis project is difficult and far-reaching precisely so it will drive me to learn a great deal about a wide range of subjects and skills. As such, it involves the need to confront some entirely new protocol, type of device, tool or aspect of design. Forward progress slows to a snails pace, frustration can surge, but eventually each area snaps into some mental focus, confidence grows and correctly operating mechanisms are the evidence of my success.<br />
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Linking the FPGA to other devices, both those built onto the Nexys2 board and the many external ones I am using, generally requires studying some protocol and set of electrical requirements, production of both soft hardware (VHDL) and physical boards, and extensive testing. There are many link protocols that can be used and I have deliberately spread my work across different ones to impel me to learn each. Serial communications, USB high speed stream mode, SPI, I2C and a 2 wire protocol proprietary to the MAX7219 chips. In addition, I had to learn how to access the DRAM chips on the Nexys2, the flash chips, and of course all the interfacing protocols for the Selectric based console and other peripherals.<br />
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In order to ensure I know how to access the various chips, I made use of a neat tool called the Bus Pirate which lets me drive and investigate the devices until I really understand the protocol. ref - <a href="http://dangerousprototypes.com/docs/Bus_Pirate">Bus Pirate site</a><br />
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<tr><td style="text-align: center;"><img alt="Buspiratev36.jpg" height="172" src="http://dangerousprototypes.com/docs/images/thumb/d/d3/Buspiratev36.jpg/150px-Buspiratev36.jpg" style="margin-left: auto; margin-right: auto;" width="320" /></td></tr>
<tr><td class="tr-caption" style="text-align: center;">Bus Pirate board</td></tr>
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The logic analyzer also lets me snapshot the activity on the lines and see glitches, timing errors and other anomalies.<br />
<br />
For the PC side, where I will emulate certain peripherals like card readers and pass the card images down to the machine, I decided to build this with a graphical interface, since I have no background in Windows GUI, and code it in Python, as I don't know that language but it appears to be worth learning.Carl Claunchhttp://www.blogger.com/profile/00359841432891565909noreply@blogger.com0tag:blogger.com,1999:blog-7951573759848963517.post-51951741930553211512013-10-30T08:40:00.000-07:002013-01-20T11:07:51.074-08:00Researching the Electronic 50 prior to adapting itThe IBM Electronic 50 is not the same mechanism as the IBM 1053 (or 2741 terminal) from the 360 era, although roughly speaking it attacks the problem the same way. It uses solenoids and microswitches for feedback, just as does the 1053, but it was redesigned more fundamentally for electronic printing.<br />
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The keyboard and the printing mechanism are separated in the E50, with the keyboard activating reed switches that are read by the logic board, not by pulling on links that select the typeball position and unclutch the print mechanism. The print mechanism is driven by the logic board, thus many actions like carriage return are done entirely differently. Shifting between upper case and lower case is done separately at the keyboard (to record in the memory whether the entered keystroke is upper case or not) and in the print mechanism (cause the typeball to rotate 180 degrees to the upper or lower case position, since printing is at a different time from entry of the text.<br />
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The most important difference for my implementation is that the position of the carriage across a line is tracked electronically, as are the tab settings. The carriage is moved right or left (called escapement) by a spiral grooved rotating rod and a photocell is used to count holes corresponding to 50ths of an inch of movement. Even when a single character is typed, the machine just rotates the escapement rod while counting holes until the carriage has moved 5 holes (for 10 character per inch pitch) or 6 holes (for 12 cpi).<br />
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Backspace is the same mechanism, but selecting 'reverse' gear and subtracting holes from the counter that tracks current carriage position. Tab is implemented by the escapement rod turning and holes being counted until the current position reaches the next 'tab' position in internal memory of the logic board. Carriage return is reverse gear, same escapement mechanism, subtracting holes until the left margin (effectively the zero position of the carriage) is reached.<br />
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The escapement rod runs at two speeds - low and high - both of which can be forward or reverse direction. Thus, carriage return or tab go into high speed mode as long as the carriage is more than 1.5" from its destination position, then drop to low speed for the final distance.<br />
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The E50 uses a 96 character ball, unlike the Selectric II type ball used in the 1130, thus is typeball incompatible. The codes for printed characters are different, necessarily, because you can't address 96 characters with the same number of tilt and rotate positions as the Selectric I and Selectric II. Thus, my adapter will have to translate from the 1130 tilt/rotate codes and commands into the appropriate codes for the E50 mechanism.<br />
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While the 1053 printer mechanism did not provide feedback to the 1130 adapter about whether it was in upper or lower case, the E50 provides such a signal using a reed switch. The 1130 adapter tracks the position it last set for case, ensuring that it does not do an upshift when the mechanism is already in upper case position, since that will jam the physical mechanism. On the E50, the solenoid for changing shift is a toggle, change to upper if in lower or change to lower if in upper, plus it reports the actual case of the mechanism via signal. Much safer design.<br />
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On the other hand, the 1053 has a microswitch to trigger the 'end of line' signal whereas the E50 depends on the logic board to track the carriage position compared to the right margin setting, not on detecting the actual carriage position. The E50 has failure modes where the logical position tracked in the counter does not match the real position of the physical carriage, and the E50 has no way of detecting that. It could type off the right end, attempt to backspace or CR past the left margin, tab to the wrong spot, mis-space, or other errant behavior.<br />
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The E50 uses two voltage levels - TTL compatible 5V for logic signals and 12V used for solenoids. Reed switches are used throughout, pulling down the signal to 0 when closing and letting pullup resistors yank it back to 1 when the switch opens. Little magnets are affixed to various mechanisms that will activate these reed switches as necessary.<br />
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The core switch in the E50 is the Print Feedback Switch. Printer actions are driven by activating the print clutch (PSCC) which rotates a rod 360 degrees, that rod powers all the tilting, hammering onto paper and other movements of the mechanism. At 85 degrees of rotation, it closes and it reopens at 300 degrees. It is used to block attempts to print another character or take an action like backspace while the mechanism is still in motion and could cause a jam. Various actions are performed at the 85 and 300 point, such as releasing the PSCC at 85 once movement has begun or turning on the escapement solenoids (plus low speed or hi speed) at 85.<br />
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The E50 supports variable velocity for the typeball striking the paper, producing more even levels of darkness by adjusting strike velocity to the character being typed. This is a fixed correspondence to the character code, which I will handle at the same time that I translate from Selectric II to E50 tilt/rotate codes.<br />
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The cables onto the logic board are well marked, thus I have already identified the wires to use to activate the PSCC (print mechanism), escapement low/high speeds, escapement reverse, index, toggle shift case, toggle ribbon color, escapement operation, photocell lamp turnon, and correction (erase character) solenoids. I also know how to read the photocell output, shift state of the carriage, print feedback switch state, and even the switch (I won't use for the 1130) that changes between 10, 12 and proportional character per inch spacing. There is a solenoid to ring the bell which I will make use of, if there is a way for 1130 programs to activate this.<br />
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The 1053 printer has separate solenoids to upshift, downshift, go to red ribbon and go to black ribbon, while the E50 simply toggles shift and toggles ribbon color, so a bit of translation and state tracking will occur. The 1130 expects two signals, CB Response and Twr Interlock, generated to let the adapter know when it is safe to request the next character or operation. CB response will be generated by the print feedback switch, while Twr Interlock will be generated any time that Escapement is on (we are still moving toward some target carriage position).<br />
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I am building a driver board that will take 3.3V logic signals and emit the 12V to activate each solenoid, plus it will level shift the reed switch TTL values down to the 3.3V logic levels of the FPGA board. Once this is complete, I can begin debugging the FGPA code that connects the E50 mechanism to the 1130 adapter.<br />
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The keyboard mechanism looks like it is adaptable for use as the keyboard of the 1130! That is, it has interposers that lock it when one key is pressed so that a second key can't be simultaneously activated. A clutch causes a cam to rotate once when a key is pressed, the cam will reset the depressed key after its value is read. The key pressed activates various reed microswitches that yield a 7 bit keycode - the E50 tilt, rotate, rack and shift bits - and these are read by the logic after it waits 5 ms from the first activation to ensure all of them have reached their stable final state. I need to look more closely at how the clutch mechanism works with the keyboard, as it may be possible to replace the clutch linkages with solenoids thus totally isolating the keyboard from the rotating motor driven parts. This would suit my needs perfectly.<br />
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Unfortunately, during my investigations, I created a tear on one side of a delicate ribbon cable that connects the logic board to the print carriage, bringing the tilt, rotate, shift, ribbon and velocity signals to that carriage. I will need to repair or replace that cable before I can proceed, but there are no spare parts or spare machines that I can locate, thus some form of repair or substitution will be necessary. This cable flexes every time the carriage moves across a line, thus the replacement or repair work needs to accommodate that hostile environment.Carl Claunchhttp://www.blogger.com/profile/00359841432891565909noreply@blogger.com0tag:blogger.com,1999:blog-7951573759848963517.post-38549759194795449902013-10-29T21:50:00.000-07:002013-01-22T14:35:54.916-08:00Designing the E50 interface to the 1130First step was to work out how to use the power supply to drive the 12V for the solenoids, which was a question mark because the power supply board had an IBM MST logic module, multiple mysteriously marked regulators and other circuitry on it, which might have required a specific handshake before delivering full power. Fortunately, I discovered that a simple bridge across two wires was enough to convince the PS to deliver full 5V and 12V power. I intend to use the 5V for the LEDs and other circuit boards that run at TTL levels, as well as the reed switch, photocell and photocell lamp inside the E50.<br />
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Having measured the resistance of the solenoid coils, I know what currents and power levels they will require and based on that, designed the driver circuit. The input is 3.3V logic levels from the FPGA, which will drive the solenoids from the 12V supply. I will prototype one of the driver circuits, verify operation and then have a board built for surface mount transistors and resistors to fit compactly into the printer enclosure.<br />
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Meanwhile, I used a lab power supply to validate the operation of the solenoids for the basic motor circuit. It was erratic turning on when the power switch was activated, caused by lubricating oil that got into the motor switch and partially burned a contact due to arcing. It was unreliable even after cleaning so I replaced it with a switch from the Selectric II typewriter I originally bought.<br />
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At this moment, the carriage is jammed at the left margin and the escapement lead screw is not turning, manually or under motor power. This also needs some investigation but the basic mechanism is clearly suitable for use as the 1130's console printer.<br />
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It was my belief that the signal listed as PUC was a switch reporting the shift status, but it is all a bit confusing, since the connector to the carriage where that signal is included does not +5V, the voltage level used with reed switches. The cable only carries ground, +12V and some control lines. My working hypothesis is that the machine does not discrete upshift and downshift solenoids, but further investigation is necessary before moving ahead on the design. The extended theory of operation manual for the E50 explicitly mentions a shift mode switch used for reporting the position of the mechanism. The diagram shows it swinging between 0V and 5V, but indicates the status at the halfway point of the PSCC rotation. Not sure if the switch maintains its 'value' when the shift movement is complete. Commanding the carrier to shift appears to require only the R2 solenoid and PSCC activation. I need to see if downshift is the same code or a different one.<br />
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Further web research suggests that the ribbon cartridge on the later Selectrics (and the Electronic xx models) did not support multiple colors, so that the shift to red and shift to black cannot be implemented. I will have those commands seem to work correctly, signalling completion at an appropriate time, to preserve programming compatibility.<br />
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I am still unable to identify the purpose of the RSH solenoid in the carriage assembly. It appears I will need to fire the solenoids to see if I can identify what each does. The tear in the ribbon cable affects only the velocity and correction solenoids. This is underway now.<br />
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A bit more testing has to be done and I must repair the ribbon cable, then I can begin testing candidate logic for my interface module.<br />
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My module has to support the tab set, tab clr, space, return and tab buttons on the console printer, as well as offering a way to set left and right margins. I am also working on the assumption that the printer operates in 10 character per inch mode, thus the scale across the front suggests a 13" wide printable line with one division of the scale covering a single character on the paper at 10 CPI.<br />
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The Electronic Model 50 is a wide platen machine, 19", which will cause difficulties fitting it inside an 1130 sized printer cover. I am not sure what I will do to address this particular issue; might have to tolerate some distortion from scale.Carl Claunchhttp://www.blogger.com/profile/00359841432891565909noreply@blogger.com0tag:blogger.com,1999:blog-7951573759848963517.post-65623569407576454602013-10-28T15:10:00.000-07:002013-01-28T22:06:24.367-08:00Testing console printer interface<div class="separator" style="clear: both; text-align: left;">
The testing plan for the console printer has three phases. First, I will use a test rig to validate the signals, timing and behavior I expect from the Electronic 50 Typewriter mechanism I leveraged, second will involve testing with the logic instantiated in the fpga 1130 but using a prototype driver board, then finally I will test the final production build of the board and connections.</div>
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<tr><td style="text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEj25D-Wut3I6rgywLzEQf3l4n0jeGX-uF5tCLhkky3pT0hkEB7_YsKHTt9txG0nPPwh7eD4cbNLDCF5kV3Fjvmw2aFYYG_MOjP3TpD3Yf5wzQLt4wSgsQD9NxOjjnjj-751RrhTQ6j9uVQ/s1600/IMG_0223.JPG" imageanchor="1" style="margin-left: auto; margin-right: auto;"><img border="0" height="239" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEj25D-Wut3I6rgywLzEQf3l4n0jeGX-uF5tCLhkky3pT0hkEB7_YsKHTt9txG0nPPwh7eD4cbNLDCF5kV3Fjvmw2aFYYG_MOjP3TpD3Yf5wzQLt4wSgsQD9NxOjjnjj-751RrhTQ6j9uVQ/s320/IMG_0223.JPG" width="320" /></a></td></tr>
<tr><td class="tr-caption" style="text-align: center;">Arduino based test rig to explore interface approach</td></tr>
</tbody></table>
<br />
Tuesday - My test rig was built with an Arduino microcontroller (Mega board) and the relay shield, giving me four relays to drive the 12V solenoid activations and a enough input pins to sense all the reed switch and photocell inputs from the E50. I put a pluggable breadboard between the Arduino rig and the E50, allowing me to change which tilt, rotate and other solenoids are selected by each relay, as well as changing other status signals from the typewriter mechanism.<br />
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<table align="center" cellpadding="0" cellspacing="0" class="tr-caption-container" style="margin-left: auto; margin-right: auto; text-align: center;"><tbody>
<tr><td style="text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEj-gFC8rSQbUpUDHk0tdQ20zJIVI7er2pUGQ2OfrW-1APFoI260DlwvQtoQmv1z9poVv6sMdcSSI1xE4rW_t7KThO16qaF75tKA_llegF67KYVIuSNKLko49sHOgQlPGprpmbFsjwFpm3Q/s1600/IMG_0224.JPG" imageanchor="1" style="margin-left: auto; margin-right: auto;"><img border="0" height="400" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEj-gFC8rSQbUpUDHk0tdQ20zJIVI7er2pUGQ2OfrW-1APFoI260DlwvQtoQmv1z9poVv6sMdcSSI1xE4rW_t7KThO16qaF75tKA_llegF67KYVIuSNKLko49sHOgQlPGprpmbFsjwFpm3Q/s400/IMG_0224.JPG" width="298" /></a></td></tr>
<tr><td class="tr-caption" style="text-align: center;">Arduino microcontroller with relay shield to drive solenoids</td></tr>
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<br />
The tilt and rotate solenoids seem stiff - dried grease from age affects many of these older machines. I will clean and lubed the entire mechanism to ensure more reliable operation. I have successfully shifted case and fired the typeball for simple characters, plus operated the mechanism that moves the carriage left and right at low and high speed. Everything is looking quite good.<br />
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<table align="center" cellpadding="0" cellspacing="0" class="tr-caption-container" style="margin-left: auto; margin-right: auto; text-align: center;"><tbody>
<tr><td style="text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEivHYpLLbPpsjXbefS0mgHWmw0pKccgKhmbisOnU8l3h1NN76jji6Z-6_HXvrWwGbqvvHk8QuqnktC76atoGSJBBesq1D2yWOTCVbHwJRzObmxXBL3RJeu7ozrZ59ox6oNa3YATQSiIGq8/s1600/IMG_0221.JPG" imageanchor="1" style="margin-left: auto; margin-right: auto;"><img border="0" height="340" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEivHYpLLbPpsjXbefS0mgHWmw0pKccgKhmbisOnU8l3h1NN76jji6Z-6_HXvrWwGbqvvHk8QuqnktC76atoGSJBBesq1D2yWOTCVbHwJRzObmxXBL3RJeu7ozrZ59ox6oNa3YATQSiIGq8/s400/IMG_0221.JPG" width="400" /></a></td></tr>
<tr><td class="tr-caption" style="text-align: center;">Driving the mechanism with my test rig</td></tr>
</tbody></table>
Steve Cook, a typewriter enthusiast and former engineer repairing these machines for IBM, kindly provided me a few key pages from the service manual, which has resolved all the questions I had about the shift mechanism, the shift status switch (yes, it is a switch that reports whether the typeball is positioned with the upper case half or lower case half facing the platen), and the mysterious looking RSH solenoid. That is the rack transfer solenoid, which selects which side for rotation from the home position. I had correctly worked out all the other signals from the connections to the removed logic board.<br />
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<table align="center" cellpadding="0" cellspacing="0" class="tr-caption-container" style="margin-left: auto; margin-right: auto; text-align: center;"><tbody>
<tr><td style="text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjtcU1qdOp8eUi3OvZChn6Hm69ScKPNSq2M9MIwN-33ySpGP-ODGVQ0JKbvy48y4llHh-KGqOxuW-hsxdLbx9vOfkv0UdNSv5cNsEi70p14ma9CZH-t2oJxuytTPUdFeJ-L5ON2lOE4fYU/s1600/IMG_0222.JPG" imageanchor="1" style="margin-left: auto; margin-right: auto;"><img border="0" height="400" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjtcU1qdOp8eUi3OvZChn6Hm69ScKPNSq2M9MIwN-33ySpGP-ODGVQ0JKbvy48y4llHh-KGqOxuW-hsxdLbx9vOfkv0UdNSv5cNsEi70p14ma9CZH-t2oJxuytTPUdFeJ-L5ON2lOE4fYU/s400/IMG_0222.JPG" width="350" /></a></td></tr>
<tr><td class="tr-caption" style="text-align: center;">Solenoids and grooved cam drum on underside of carriage</td></tr>
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<table align="center" cellpadding="0" cellspacing="0" class="tr-caption-container" style="margin-left: auto; margin-right: auto; text-align: center;"><tbody>
<tr><td><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEgXrkdWrRCMDwhfJIZOB6yhIMmAfAeLf18iqT6qp6DKm7NVqqj8HufrwCIcv6s0nfLFH7nUDtxhTSvUDoMFNv_WgkeIuIOhyphenhyphenqr_enmgn7eeh-Ro8Dw-O5k-V61mjBahziWJUyb5Ml5VEso/s1600/IMG_0210.JPG" imageanchor="1" style="margin-left: auto; margin-right: auto;"><img border="0" height="400" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEgXrkdWrRCMDwhfJIZOB6yhIMmAfAeLf18iqT6qp6DKm7NVqqj8HufrwCIcv6s0nfLFH7nUDtxhTSvUDoMFNv_WgkeIuIOhyphenhyphenqr_enmgn7eeh-Ro8Dw-O5k-V61mjBahziWJUyb5Ml5VEso/s400/IMG_0210.JPG" width="298" /></a></td></tr>
<tr><td class="tr-caption" style="font-size: 13px;">Logic board of E50 - not used in this project</td></tr>
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<div>
I should receive the components for the driver board tomorrow, whence I can build a prototype single driver, verify the design and then fire off an order for a PCB to mount under the typewriter frame in place of the existing logic board. As an added bonus, the power supply from the E50 will give me all the clean 5V power I need to drive the LEDs in the console display panel and other places on the replica 1130.<br />
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<table align="center" cellpadding="0" cellspacing="0" class="tr-caption-container" style="margin-left: auto; margin-right: auto; text-align: center;"><tbody>
<tr><td style="text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEiiFqC4llsQHOI24Qdf0qkf3I0uuI6WBD_QZAopJLEgo-uadDB_UOoQtbFesE73zmU11nB0f0J6KsPXzK2zLOzV6jP7-k_4RKyGzQzTujBkKaRDLJH5SpC4kYUOlINmvuGPXGauPM7uUDQ/s1600/IMG_0217.JPG" imageanchor="1" style="margin-left: auto; margin-right: auto;"><img border="0" height="298" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEiiFqC4llsQHOI24Qdf0qkf3I0uuI6WBD_QZAopJLEgo-uadDB_UOoQtbFesE73zmU11nB0f0J6KsPXzK2zLOzV6jP7-k_4RKyGzQzTujBkKaRDLJH5SpC4kYUOlINmvuGPXGauPM7uUDQ/s400/IMG_0217.JPG" width="400" /></a></td></tr>
<tr><td class="tr-caption" style="text-align: center;">E50 Power Supply - 12V for E50 and 5V for my other logic boards</td></tr>
</tbody></table>
The machine is quite messy, with excess oil in places it doesn't belong, sticky partially dried lubricant in places that should have fresh oil or grease, and the universal problem with the IBM typewriters of disintegrating foam inside. Soundproofing becomes a viscous tarry substance or shreds and floats into places it shouldn't be. I am going to clean it off with isopropyl alcohol then lubricate it properly - that should improve performance and reliability.<br />
<br />
Wednesday - After about six hours of scraping off the soundproofing, then cleaning and relubricating the typewriter, I am ready to resume testing of my interface. I had to pick up the appropriate oil (Mobil 1 0W-20), grease (Mobile 1 synthetic) and cleaning supplies in order to finish the cleanup. I have my driver board parts, but they are very tiny surface mount parts (e.g. 0805 size resistors), which are harder to prototype without creating the board first. Will run tomorrow out to find some kind of prototyping board suitable for mounting the transistor, but use old school style full sized resistors for ease of construction. Should finish up the prototype and test Thursday, plus the design of the production board and send it off to be manufactured.<br />
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<table align="center" cellpadding="0" cellspacing="0" class="tr-caption-container" style="margin-left: auto; margin-right: auto; text-align: center;"><tbody>
<tr><td style="text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEh63ziTdzNeYjLUJoc1KwMEjvCUL6dfmAmYQu5WQ_5ics3mBGpLmiOG2rlk45MuWTgkMYHhM20EynbLBRkY4pVUjKU3v8bpnyvma7N89x3R7E4V0EeSXVI9ejOgZIhWWUMaw0oX5vs0OOI/s1600/IMG_0225.JPG" imageanchor="1" style="margin-left: auto; margin-right: auto;"><img border="0" height="320" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEh63ziTdzNeYjLUJoc1KwMEjvCUL6dfmAmYQu5WQ_5ics3mBGpLmiOG2rlk45MuWTgkMYHhM20EynbLBRkY4pVUjKU3v8bpnyvma7N89x3R7E4V0EeSXVI9ejOgZIhWWUMaw0oX5vs0OOI/s320/IMG_0225.JPG" width="239" /></a></td></tr>
<tr><td class="tr-caption" style="text-align: center;">Circuit prototype for solenoid driver for E50</td></tr>
</tbody></table>
<br />
Friday - Prototype tested, works very well, thus on to PCB ordering. Having my set of challenges forcing the PCB design software to produce clean output - it keeps placing signal lines or vias (holes connecting signals on different layers of the board) on top of each other, touching components or overlapping the lettering/outlines of the silkscreen layer. Finally produced clean design files and shopping around for best combination of price and delivery time.<br />
<br />
Sunday - finished and ordered the PCB boards to manage button and switch inputs and the LED outputs. It took lots of thought and hand routing to get the connections made among the fourteen chips and other parts. The automatic routing built into the PCB software was unable to converge on a solution, forcing me into manual mode. The other boards, for the LED panel and typewriter solenoid drivers, were easily handled by the automatic routing algorithm and needed just a few hours of tweaking to get into production ready state.<br />
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<tr><td style="text-align: center;"><img height="400" src="http://uploads.oshpark.com/uploads/project/bottom_image/HyGB7sfX/thumb_i.png" style="margin-left: auto; margin-right: auto;" width="264" /></td></tr>
<tr><td class="tr-caption" style="text-align: center;">Bottom side of input control board PCB I designed</td></tr>
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<tr><td style="text-align: center;"><img height="400" src="http://uploads.oshpark.com/uploads/project/top_image/HyGB7sfX/thumb_i.png" style="margin-left: auto; margin-right: auto;" width="264" /></td></tr>
<tr><td class="tr-caption" style="text-align: center;">Top side of the input control PCB I submitted to the fab</td></tr>
</tbody></table>
My boards are using surface mount components, which are difficult to solder by hand, so I have bought the parts to build my own solder reflow oven, where I can place all the parts into solder paste on the board at once, then heat it in the oven with the proper temperature ramp, causing the solder to melt, pull the parts into proper alignment and then cool to hardened high quality solder connections. I should have the oven completed by Tuesday evening. I am using a PID controller (proportional integral derivative) with a thermocouple, tied to a solid state relay to modulate the heat in an inexpensive toaster oven. It is essential to follow a specific heat profile, set by the maker of the solder paste being used, to produce good solder joints:<br />
<br />
- first, the board temperature is raised slowly to almost the melting point of solder, typical target rates are 1-2 degrees C per second.<br />
<br />
- next it is raised a bit and held steady to boil off the flux and clean the surfaces that will be bonded, long enough to eliminate any voids that may form around air bubbles or liquid flux. A representative soak phase is about a minute.<br />
<br />
- the oven should then move the temperature up quickly to a safe margin above the melting point of the solder paste being used, which then flows over the bonding surfaces. Surface tension of the liquified solder will pull the solder away from the gaps between pads and will drag components into alignment with the pad to which they are being attached. The time to complete this step may also be one minute long.<br />
<br />
- the board is then cooled at a moderate pace to minimize thermal shock, causing the solder to solidify. Once cool enough, it is removed and checked to ensure all joints are properly done, perhaps cooling at 2 C per second.<br />
<br />
The solder is in a paste that is smeared on the pads, then each part is pushed into the paste where it sits waiting for the melting phase inside the oven. Because solder, flux and the components contain materials like lead that are unhealthy, the oven can never be used for food. I will mark it as contaminated by hazardous materials to avoid inadvertent misuse in the future.<br />
<br />
After a bit of practice with the reflow oven, I will wait for my boards to come back from the manufacturers (Oshpark and Sunstone) then assemble them. All of the components to install on the boards are on their way from Digikey or already on hand. </div>
Carl Claunchhttp://www.blogger.com/profile/00359841432891565909noreply@blogger.com0tag:blogger.com,1999:blog-7951573759848963517.post-7938219086857282272013-10-27T17:16:00.000-07:002013-01-29T17:17:21.818-08:00Great start on keyboard realism with ebay purchaseThe keyboard used with the 1130 is the mechanical keyboard from the 029 keypunch, which has quite a different feel from the microswitch based keyboards of present day systems. The 1130 used the same shape and coloring as the 029 keys, with slightly differences in the number of keys and their assignment.<br />
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<table align="center" cellpadding="0" cellspacing="0" class="tr-caption-container" style="margin-left: auto; margin-right: auto; text-align: center;"><tbody>
<tr><td style="text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEiotsOkNN1LB6H4Rmu1t4ykeHOKAPOWf1sQAQ2U1HPnpJ9H4iPgxllMiUbd8ZLfJbhLSfTXJZpsXR4XPH16iOd0yPiPcT-9iluXwh3FUjPQWA5KQZ74T5hd4PBxyIGLJllziTpN5wxQ7CM/s1600/keyboard+and+switches+only.jpg" imageanchor="1" style="margin-left: auto; margin-right: auto;"><img border="0" height="122" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEiotsOkNN1LB6H4Rmu1t4ykeHOKAPOWf1sQAQ2U1HPnpJ9H4iPgxllMiUbd8ZLfJbhLSfTXJZpsXR4XPH16iOd0yPiPcT-9iluXwh3FUjPQWA5KQZ74T5hd4PBxyIGLJllziTpN5wxQ7CM/s400/keyboard+and+switches+only.jpg" width="400" /></a></td></tr>
<tr><td class="tr-caption" style="text-align: center;">IBM 1130 keyboard</td></tr>
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<table align="center" cellpadding="0" cellspacing="0" class="tr-caption-container" style="margin-left: auto; margin-right: auto; text-align: center;"><tbody>
<tr><td style="text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEhz4XfmxhcfNaMJscM9LQVIVYqNRh8rb59-_R_EAonJ1Nvw2M6yZXPBDsAuf_X9gvFAdMER2EU31lXJOeq3A_90QB8gQmFMxpvTscBluO9y9n6RHicAoEKi5tZQr0-PU2BU9bylw90c7fA/s1600/keypunch-kbd2.jpg" imageanchor="1" style="margin-left: auto; margin-right: auto;"><img border="0" height="109" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEhz4XfmxhcfNaMJscM9LQVIVYqNRh8rb59-_R_EAonJ1Nvw2M6yZXPBDsAuf_X9gvFAdMER2EU31lXJOeq3A_90QB8gQmFMxpvTscBluO9y9n6RHicAoEKi5tZQr0-PU2BU9bylw90c7fA/s320/keypunch-kbd2.jpg" width="320" /></a></td></tr>
<tr><td class="tr-caption" style="text-align: center;">Keyboard from an IBM 029 Keypunch</td></tr>
</tbody></table>
<br />
I came across a keyboard on Ebay that was from a data entry system that competed with the IBM 029 and 129 products, thus it was modeled closely on the look and feel of the IBM version. This is an excellent basis upon which to build my 1130 replica keyboard.<br />
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<table align="center" cellpadding="0" cellspacing="0" class="tr-caption-container" style="margin-left: auto; margin-right: auto; text-align: center;"><tbody>
<tr><td style="text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEiE-gCFZvGnP1slX4PnYea7pq36XcI4d4iyIF4-ArrYf-wRFsh_-E7O0au3NWrr5XTORefFb5Pnd0ddrbWCmp0ZU2bdyIitEsu2BPDCnN8JpzM510KoOb5sGEFT4XKvQRPaRkR_ZjFGmJs/s1600/kb1.jpg" imageanchor="1" style="margin-left: auto; margin-right: auto;"><img border="0" height="298" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEiE-gCFZvGnP1slX4PnYea7pq36XcI4d4iyIF4-ArrYf-wRFsh_-E7O0au3NWrr5XTORefFb5Pnd0ddrbWCmp0ZU2bdyIitEsu2BPDCnN8JpzM510KoOb5sGEFT4XKvQRPaRkR_ZjFGmJs/s400/kb1.jpg" width="400" /></a></td></tr>
<tr><td class="tr-caption" style="text-align: center;">Ebay keyboard I acquired for use with 1130 project</td></tr>
</tbody></table>
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<table align="center" cellpadding="0" cellspacing="0" class="tr-caption-container" style="margin-left: auto; margin-right: auto; text-align: center;"><tbody>
<tr><td style="text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjLUGQfJuMDliwXXTqDZu3K_AkmT5jGaJ8HOjAgByC6ayw-Xq_I6qWGF68zi9gs-k3Tp1ecYK5Po-mEDJ5yWBpMv8daNNmhyphenhyphen9AR-ivFQxUUwLg4u04-6xQcjPlJ6stJe8wwmqx2BsJh6Gs/s1600/kb2.jpg" imageanchor="1" style="margin-left: auto; margin-right: auto;"><img border="0" height="298" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjLUGQfJuMDliwXXTqDZu3K_AkmT5jGaJ8HOjAgByC6ayw-Xq_I6qWGF68zi9gs-k3Tp1ecYK5Po-mEDJ5yWBpMv8daNNmhyphenhyphen9AR-ivFQxUUwLg4u04-6xQcjPlJ6stJe8wwmqx2BsJh6Gs/s400/kb2.jpg" width="400" /></a></td></tr>
<tr><td class="tr-caption" style="text-align: center;">Another view of the keyboard from ebay</td></tr>
</tbody></table>
The keyboard does not use the mechanical bail switch decoding mechanism of the IBM versions, instead it uses photocells to detect keypresses. As you can see, the colors are slightly different, most obvious with the darker grey in my unit, but this is well within the bounds of human memory for absolute hues, meaning that it will be perceived to be the same as the 1130 version unless compared directly. This is especially true for most people who will have only a past memory of the actual keyboard.<br />
<br />
I will need to do some investigation once it arrives to discover how to identify keypresses, then build my interface logic to translate this to 1130 keyboard behaviors. Fortunately, there is a patent for the mechanism that provides some insight into its construction and use. The interface looks super simple to create. Further, the mechanism seems to provide the latching, need to restore and other characteristics that I want my keyboard to exhibit, so as to be quite reminiscent of the IBM 1130 keyboard. I have included a diagram from the patent here to illustrate the suitability of this keyboard for my purpose.<br />
<table align="center" cellpadding="0" cellspacing="0" class="tr-caption-container" style="margin-left: auto; margin-right: auto; text-align: center;"><tbody>
<tr><td style="text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjgC4LLFXhUPfzPMUwnvJ8DN7RTqr4xytiUjdhgCfisL1eH8X1gr2DiMMCBhv4h6_JPoHa4UZocoavj79SN_jWWkgsKkDUb5hpx22JLSGfXNBrKY5UNUV3BuZhhi5d0gM7BdyMsIl6e6Nw/s1600/kb3.jpg" imageanchor="1" style="margin-left: auto; margin-right: auto;"><img border="0" height="141" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjgC4LLFXhUPfzPMUwnvJ8DN7RTqr4xytiUjdhgCfisL1eH8X1gr2DiMMCBhv4h6_JPoHa4UZocoavj79SN_jWWkgsKkDUb5hpx22JLSGfXNBrKY5UNUV3BuZhhi5d0gM7BdyMsIl6e6Nw/s400/kb3.jpg" width="400" /></a></td></tr>
<tr><td class="tr-caption" style="text-align: center;">Diagram from US patent 3,092,310 granted June 1963 </td></tr>
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.Carl Claunchhttp://www.blogger.com/profile/00359841432891565909noreply@blogger.com0tag:blogger.com,1999:blog-7951573759848963517.post-84852083318404983082013-10-26T11:55:00.000-07:002013-02-03T21:40:10.922-08:00Creating reflow oven to build printed circuit boardsPrinted circuit boards have evolved from using components whose pins or wire leads fit through a hole in the board, to use of surface mount devices that do not require any hole. These permit boards to be composed of many layers practically, because the pins/wires of the devices are not interfering with any of the layers other than the top one that contains the component. This has been accompanied by the continual shrinking of the size of these components, all of which makes hand-soldering more and more difficult. Since the mainstream uses these surface mount devices (SMD), manufacturers of chips and other parts have shifted to SMD. It is impossible to get certain chips in a traditional, non-SMD packaging. Such is the case for a few chips that were ideal for use in my project.<br />
<br />
Factory production of PCBs make use of reflow, where all the components are soldered to the board in a single pass. In one method, the devices placed on their intended copper connection pads with a sticky solder paste, then heated in an oven with a careful ramp up and cooldown process that minimizes thermal shock to the parts while producing excellent connections. The boards are placed in a reflow oven to heat and cool them. Commercial ovens are many thousands of dollars, but hobbyists have found ways to produce workable ovens for under $100 - I took on such a project to deal with the boards I am creating for the 1130 project.<br />
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I leveraged an old case I had in my garage, placing the circuitry for my oven into it. I bought an inexpensive 1500W toaster oven to use - the boards and solders contain lead and other elements that are not good to ingest - even being absorbed from the fingers at low rates. This will never be used to prepare food, because it is now contaminated by lead, bismuth and other metals.<br />
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<tr><td style="text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjmtM_vXiYTyUwD8DgQRLPFkSOeWQCxeGlkvuzAZ1GG-XZfa8WCs1b42c52ctTYdeQW2zJdIAg_akgXdYMomKxA9AlGHwAvT7qqbBC44FLEKvLUgA1vcoW-G0sGMBuZHIEaBbrp65zH6NY/s1600/IMG_0228.JPG" imageanchor="1" style="margin-left: auto; margin-right: auto;"><img border="0" height="233" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjmtM_vXiYTyUwD8DgQRLPFkSOeWQCxeGlkvuzAZ1GG-XZfa8WCs1b42c52ctTYdeQW2zJdIAg_akgXdYMomKxA9AlGHwAvT7qqbBC44FLEKvLUgA1vcoW-G0sGMBuZHIEaBbrp65zH6NY/s400/IMG_0228.JPG" width="400" /></a></td></tr>
<tr><td class="tr-caption" style="text-align: center;">My reflow oven and controller</td></tr>
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I inserted a temperature probe (thermocouple) into the oven and removed the power plug from the end of the cable. In the old case to the left, I inserted a PID controller, SSR and the power cable from the toaster oven. I wired them up and put on a power cable with plug. The PID controller is a unit that will get the oven to a selected temperature and hold it there very accurately.<br />
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The name PID stands for proportional integral derivative - but the essence is that this is a smart controller that looks at feedback from the probe and figures out how to provide power to the oven to reach and hold the temperature.<br />
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<tr><td style="text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEhvIqxECXRw5eQqO-oQLV-54jEyj_Lsq6GCtmOaysCQBnbJHnOu8REvxTQMnDWJzFLBvHra7XZi5F94SS032fZ5kFQ2PDOkKxFzfNAXctqyWTMAy9v1e_nNCFgGUJfVAznIXZveCHI-O7c/s1600/IMG_0230.JPG" imageanchor="1" style="margin-left: auto; margin-right: auto;"><img border="0" height="355" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEhvIqxECXRw5eQqO-oQLV-54jEyj_Lsq6GCtmOaysCQBnbJHnOu8REvxTQMnDWJzFLBvHra7XZi5F94SS032fZ5kFQ2PDOkKxFzfNAXctqyWTMAy9v1e_nNCFgGUJfVAznIXZveCHI-O7c/s400/IMG_0230.JPG" width="400" /></a></td></tr>
<tr><td class="tr-caption" style="text-align: center;">PID controller to hold the oven at a target temperature</td></tr>
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The SSR is a solid state relay, a device that will switch the power to the toaster oven on and off as needed. In operation, the PID is usually pulsing or cycling the power to the oven, which you see by the light on the oven flashing on and off.<br />
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As the oven approaches the right temperature, the light flickers on for shorter and shorter periods. If it simply stayed on till hitting the temperature, the glowing heating elements in the over would keep adding heat as they cooled, pushing the temp inside the oven way over the target before the elements cooled all the way down. The controller autotunes itself, learning how to 'sneak up on' the right temp by lowering the heat of the elements at the right rate.<br />
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I put a thin layer of solder paste on the copper pads where devices should be soldered. The device plops into the paste and is held on the board by the stickiness of the gooey paste. The board goes in the oven and begins heating. When the paste gets hot enough, the goo part, which is called flux, melts and evaporates. This cleans off metal corrosion and dirt from the metal surfaces, ensuring that the solder can bond. The heat goes up gradually enough to make sure that the flux is fully evaporated before turning the metal part of the paste into flowing solder - otherwise air bubbles might cause poor solder joints.<br />
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The solder paste then reaches its liquification temperature and flows. Surface tension of the liquid solder causes it to form a bulging surface on the copper pads and device pins, while sucking away from the non metal part of the board. This puts the solder on each pin where it belongs and not bridging between the pins. As an added bonus, the power of the surface tension will pull the component into alignment, so that it does not need to be placed with extreme precision before soldering.<br />
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The designer of a PCB will usually have a 'stencil' made from the design of the top layer - generating a plastic sheet with openings where paste should be applied atop copper pads. This is placed atop the naked PCB, paste is then applied with a squeegee like tool (like a putty knife) to produce the right depth of paste on each pad. This adds $10 or more to each board designed, thus some will apply the paste without the guidance of a stencil.<br />
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I bought some junk circuit boards and surplus SMD chips at a local electronics shop to practice with, and have worked out the right amount of paste and timing for my oven. This was tricky to get right. Too much paste and a big ball of solder formed, which would bridge more than one pin if the SMD device had very small, closely packed pins. Too little and it didn't reliably form solder joints nor pull the device into alignment. Fortunately, the minimum amount is not that sensitive, even pretty thin swipes yielded satisfactory joints as long as the device was fairly well aligned.<br />
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Not using a stencil produces some waste goo placed on undesired spots of the PCB, which yields teeny dots of solder to flake off after using the oven. Since a 5cc syringe of solder paste is about $15, waste costs money as well as inconvenience. If solder bridges do form because of too much paste, they can be fixed by a process called 'reword' where you place a copper braid onto the blog while heating it, the copper braid will suck off the excess solder (wicking it up the same way that the wick of a candle will draw molten wax up to the tip of the wick where it burns). One tries to minimize the need for rework, as each application of heat shocks the parts and potentially could lead to some damage to teeny pins if I move them too much during fixes.<br />
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Another interesting problem concerns boards that are designed to mount parts on both the 'top' and 'bottom' faces of the PCB. If you solder one side, then flip the board over and solder the second face, the solder on the bottom is becoming molten again during the second pass in the oven. The parts might drop off or shift out of alignment. This is solved various ways in production, often by putting a tiny dot of epoxy glue under each component that will go on the 'bottom' face when the board is soldered a second time. The heat of the oven causes the epoxy to harden at the same time that the solder is molten, thus the part won't fall off even if the solder is melted the second time in the oven since the glue stays firm.<br />
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I have a different way to approach this, based on the availability of different solder pastes with different temperature profiles. My plan is to solder the 'bottom' face components using a paste with a higher melting point. When I flip the board to solder parts on the other side, I use a lower temperature paste. If the oven never gets hot enough to melt the solder on the bottom parts, then they will not fall off! Commonly available pastes have more than 200 degrees F difference in melting points, far more than the inaccuracies in my temperature control of the oven.<br />
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Now I am ready to solder the parts onto my 1130 printed circuit boards using the low temp paste, as soon as they arrive from the PCB manufacturer. With some practice learning how to use the normal (high) temperature paste, I can do the double sided component placement for my 'input controller' board since I put integrated circuits and other parts on both faces to simplify the wire routing.<br />
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My first PCB arrived today - it was a 2 day turnaround which skipped several steps that the others will include, such as the green colored 'solder mask' that insulates and protects all but the copper pads where parts are soldered, and it does not have the printed outlines and labels for parts (silkscreen layer). Functionally, it is fine for the purpose - it is a card that I will install inside the typewriter to interface it properly to my system. It has drivers that will activate the solenoids under control of the FPGA board.<br />
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<tr><td style="text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEgq063X_BN63SVTQu8ahodCKx5G7m6Wnp7oR-HFH-qn3Nk4rSTv5d84lzFQaLrdU0vVTNe0ysAqTGMiEXdjjwcSDduxvAGXHmOLliRvTQzfFMPXZqzqhtJURxNJXucz3RqLBoeon2t-U4w/s1600/IMG_0231.JPG" imageanchor="1" style="margin-left: auto; margin-right: auto;"><img border="0" height="298" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEgq063X_BN63SVTQu8ahodCKx5G7m6Wnp7oR-HFH-qn3Nk4rSTv5d84lzFQaLrdU0vVTNe0ysAqTGMiEXdjjwcSDduxvAGXHmOLliRvTQzfFMPXZqzqhtJURxNJXucz3RqLBoeon2t-U4w/s400/IMG_0231.JPG" width="400" /></a></td></tr>
<tr><td class="tr-caption" style="text-align: center;">My solenoid driver board as it came from the fab</td></tr>
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I installed the parts (other than the connectors for the edge because they would make it hard for the PCB to sit evenly in the oven), using the solder paste, then put it into the reflow oven and presto - perfectly soldered board.<br />
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<tr><td style="text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjXJ6sEELBs3p63DdwgXiZfs5hZlRPQIqAx_IRs-9KwF6ZAomAqByciKjHprvyHY5qIizByTXPb4jTLd-SkkAVgDLPVqolcwdALq_0vNXBwr94GkiS2XXWxc8VZGeTM6-wtn1gp-v8cR44/s1600/IMG_0232.JPG" imageanchor="1" style="margin-left: auto; margin-right: auto;"><img border="0" height="162" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjXJ6sEELBs3p63DdwgXiZfs5hZlRPQIqAx_IRs-9KwF6ZAomAqByciKjHprvyHY5qIizByTXPb4jTLd-SkkAVgDLPVqolcwdALq_0vNXBwr94GkiS2XXWxc8VZGeTM6-wtn1gp-v8cR44/s400/IMG_0232.JPG" width="400" /></a></td></tr>
<tr><td class="tr-caption" style="text-align: center;">Parts pushed into solder paste and the board is being heated</td></tr>
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Unfortunately I had miscounted my parts and was short two resistors, so when I pick some up tomorrow I will hand solder the remaining two onto the board. The resistors are about the size of a flea, very easy to lose and challenging to pick up with the tweezers and put into place - think about how hard it will be to solder it on.<br />
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<tr><td style="text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEiCn7TJGtoXs40THjmAX14G3QqyRJgh7bU7PXIYmWYxvecY6n8CHakFV18MDZXkgV5Hr8UEVO3j-pbGu1s9rb9L4AxIyM1RrEq_mVEmwRPgih3QzfJ4-E7ks2WXIZEfAlnCTP4FkNVy7L0/s1600/IMG_0233.JPG" imageanchor="1" style="margin-left: auto; margin-right: auto;"><img border="0" height="298" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEiCn7TJGtoXs40THjmAX14G3QqyRJgh7bU7PXIYmWYxvecY6n8CHakFV18MDZXkgV5Hr8UEVO3j-pbGu1s9rb9L4AxIyM1RrEq_mVEmwRPgih3QzfJ4-E7ks2WXIZEfAlnCTP4FkNVy7L0/s400/IMG_0233.JPG" width="400" /></a></td></tr>
<tr><td class="tr-caption" style="text-align: center;">Done with heating cycle, everything soldered down</td></tr>
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The connectors were placed once the board cooled down, and soldered in, after which I did a full test of the connections. Everything looks great!<br />
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<tr><td style="text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEgOeKzaVaJEdI8HNrX4_t5Iywto4iJUkiqU9CWPaGWOhTV-5UeBdNr071szrHpB9kIJaDp66Nxtxynd8N3V8C0xALfcHhvzYmtkEEgfeAfSHJsuwvQS6bcTP7uTxsYTdkHqvAeSt-aZ51I/s1600/IMG_0234.JPG" imageanchor="1" style="margin-left: auto; margin-right: auto;"><img border="0" height="298" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEgOeKzaVaJEdI8HNrX4_t5Iywto4iJUkiqU9CWPaGWOhTV-5UeBdNr071szrHpB9kIJaDp66Nxtxynd8N3V8C0xALfcHhvzYmtkEEgfeAfSHJsuwvQS6bcTP7uTxsYTdkHqvAeSt-aZ51I/s400/IMG_0234.JPG" width="400" /></a></td></tr>
<tr><td class="tr-caption" style="text-align: center;">Board finished except for the missing two tiny resistors</td></tr>
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After I bought some extra resistors, I hand soldered them and had a completed board. The resistors are the small rectangles you see to the side of the transistors which are the larger dark rectangles. They are normal size for surface mount resistors, a mere .08" long by .05" wide, but the parts can be as small as 1/100 of an inch long. Tweezers and a steady hand are necessary to work with them.<br />
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It was plugged into the typewriter and I am beginning to run some candidate logic sequences to verify that I am driving the operations correctly, such as carriage return, line feed, shift case, tab, and of course typing letters. So far, it is working exactly as I expected. Need to complete my fpga logic module then kick off detailed testing.<br />
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Sometime this weekend I will spray the board with a protectant seal, using a silcone conformal spray, similar to the solder masks on modern boards but also protecting the components on the board. That will keep it in good order when mounted underneath the typewriter mechanism, subject to vibration, heat and grease/oil drippings.<br />
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<tr><td style="text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEj5dg0vUcpy-CjijjG2FH-RgG0f90tJTfoWXP598f_kOUxSsvnFX_uQRCww-kIceKza8KUPf1Ru0bEz2frFiPpzxO5rUhJAk8koZMPksGdR0FwRElzlqdPA4KTKOWS1RK3w5Qlsd_lPYaA/s1600/IMG_0235.JPG" imageanchor="1" style="margin-left: auto; margin-right: auto;"><img border="0" height="298" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEj5dg0vUcpy-CjijjG2FH-RgG0f90tJTfoWXP598f_kOUxSsvnFX_uQRCww-kIceKza8KUPf1Ru0bEz2frFiPpzxO5rUhJAk8koZMPksGdR0FwRElzlqdPA4KTKOWS1RK3w5Qlsd_lPYaA/s400/IMG_0235.JPG" width="400" /></a></td></tr>
<tr><td class="tr-caption" style="text-align: center;">Finished board with coating, ready for installation</td></tr>
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The board is mounted on the underside below the space where the carriage travels, in the place that the IBM logic board was mounted before I began the conversion. Besides the cables connecting the board to the typewriter mechanism (most are connected in the picture below), there are several cables that will link this to the FPGA 1130 board and power feeds on the side delivering clean 5V and 12V power for use by other logic boards.<br />
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<tr><td style="text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEhHptELi0Yx818z7u4Hq4vyCenYuVd7bAmvv3lyac3mWj9R7HeiVfO8nRH1NsjFZ0R81JigXt8l8UElRCcn2vi8rUKKdhASMWCE4ZObr8ricv8d0g_5l18P6k67qBypnYdWcxYkC3QpfuA/s1600/IMG_0236.JPG" imageanchor="1" style="margin-left: auto; margin-right: auto;"><img border="0" height="220" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEhHptELi0Yx818z7u4Hq4vyCenYuVd7bAmvv3lyac3mWj9R7HeiVfO8nRH1NsjFZ0R81JigXt8l8UElRCcn2vi8rUKKdhASMWCE4ZObr8ricv8d0g_5l18P6k67qBypnYdWcxYkC3QpfuA/s400/IMG_0236.JPG" width="400" /></a></td></tr>
<tr><td class="tr-caption" style="text-align: center;">My board installed in place of IBM E50 logic board</td></tr>
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<br />Carl Claunchhttp://www.blogger.com/profile/00359841432891565909noreply@blogger.com0tag:blogger.com,1999:blog-7951573759848963517.post-24365594402299848012013-10-24T13:06:00.000-07:002013-02-11T09:09:36.971-08:00Highlighting a similar project - 360/30 recreationRecently, I received an email from Lawrence Wilkinson who discovered my blog. He has a similar project, building a replica 360/30 mainframe which is contemporaneous to the 1130 system and shares the technology and many design elements. <a href="http://www.ljw.me.uk/ibm360/vhdl/">View his project website</a> for more on his effort.<br />
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We have made very parallel choices in design and approach for our two projects, almost eerie as I can easily imagine perfectly reasonable alternate selections that could have been made. He and I are currently wrestling with the console typewriters, a modified version of the Selectric typewriter, which is another unlikely coincidence.<br />
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His talk at the April OSHUG meeting ( <a href="http://skillsmatter.com/podcast/ajax-ria/computer-conservation-with-fpgas">Lawrence Wilkinson's talk</a> ) shared the background and demonstrated the state of the machine. He is mainly working now on building out peripherals, such as the console typewriter and a disk drive emulation, with the aim of successfully IPLing (booting up) the DOS/360 operating system by April of 2014, although he is also slowly building a physical console to replace the VGA screen that serves the purpose today.<br />
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I expect we will be sharing ideas and designs on our respective projects and on related matters. With these older computing systems becoming historical artifacts, the real examples disappearing from the planet due to age, projects such as ours will be helpful both as examples of what the machines were like and as advisory resources to those restoring real machines in museums around the world.Carl Claunchhttp://www.blogger.com/profile/00359841432891565909noreply@blogger.com0